Project Information                                         c:\bean\toplev.rpt

MAX+plus II Compiler Report File
Version 7.0 08/26/96
Compiled: 09/08/97 13:02:59

Copyright (c) Altera Corporation, 1996. This file may contain proprietary and confidential
information of Altera Corporation that may be used, copied, and disclosed only pursuant to
the terms of Altera's Program License Agreement. Altera makes no claim to any end-user or
third-party proprietary information that also may be contained in this file. This notice
must be contained as part of this text at all times.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

toplev    EPM7128ELC84-10  17       39       0      112     0           87 %

User Pins:                 17       39       0  



Project Information                                         c:\bean\toplev.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 86, File c:\bean\ram.tdf:
   Group range ai[0..2] differs from declaration ai[4..0]
Warning: Line 12, File c:\bean\ram.tdf:
   Symbolic name "ai3" was declared but never used


Project Information                                         c:\bean\toplev.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'PCLK' chosen for auto global Clock
INFO: Signal '2xPCLK' chosen for auto global Clock
INFO: Signal '/RESET' chosen for auto global Clear


Project Information                                         c:\bean\toplev.rpt

** PIN/LC/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

toplev@27                         /AACK
toplev@LC39                       |abus:127|addr_state~1
toplev@LC36                       |abus:127|addr_state~2
toplev@LC34                       |abus:127|addr_state~3
toplev@81                         ACIA/CS
toplev@73                         ACIA_RS
toplev@76                         ACIA_R/W
toplev@11                         Addr_In_o
toplev@12                         Addr_In_z
toplev@9                          Addr_In0
toplev@10                         Addr_In1
toplev@17                         Addr_In2
toplev@46                         Addr_In3
toplev@8                          Addr_In4
toplev@25                         Addr_Latch
toplev@23                         Addr_Out0
toplev@62                         Addr_Out1
toplev@31                         Addr_Out2
toplev@52                         Addr_Out3
toplev@49                         Addr_Out4
toplev@64                         BYTE_LANE0
toplev@65                         BYTE_LANE1
toplev@67                         BYTE_LANE2
toplev@69                         BYTE_LANE3
toplev@54                         BYTE_LANE4
toplev@58                         BYTE_LANE5
toplev@57                         BYTE_LANE6
toplev@60                         BYTE_LANE7
toplev@29                         /CAS0
toplev@41                         /CAS1
toplev@34                         /CAS2
toplev@39                         /CAS3
toplev@33                         /CAS4
toplev@35                         /CAS5
toplev@37                         /CAS6
toplev@40                         /CAS7
toplev@48                         C/R_MUX
toplev@24                         /CS_IO
toplev@74                         /CS_RAMIO1
toplev@75                         /CS_RAMIO2
toplev@28                         /CS_ROM
toplev@79                         /CS_ROM2
toplev@LC97                       |dbus:129|data_state~1
toplev@LC109                      |dbus:129|data_state~2
toplev@18                         E_CLOCK
toplev@LC20                       |io:162|E_clock~1
toplev@LC19                       |io:162|E_clock~2
toplev@LC23                       |io:162|E_clock~3
toplev@LC69                       |io:162|io_state~1
toplev@LC68                       |io:162|io_state~2
toplev@LC77                       |io:162|io_state~3
toplev@LC86                       |io:162|XR_clock~1
toplev@LC15                       |io:162|XR_clock~2
toplev@LC28                       |io:162|XR_clock~3
toplev@LC41                       LTSIZ0
toplev@LC42                       LTSIZ1
toplev@LC44                       LTSIZ2
toplev@14                         LTT1_2
toplev@30                         LTT1
toplev@83                         PCLK
toplev@LC27                       |ram:132.ao3
toplev@LC18                       |ram:132|B_COUNT1
toplev@LC17                       |ram:132|CAS_FF
toplev@LC113                      |ram:132.ram_refresh
toplev@LC22                       |ram:132|ram_state~1
toplev@LC26                       |ram:132|ram_state~2
toplev@LC30                       |ram:132|ram_state~3
toplev@LC29                       |ram:132|ram_state~4
toplev@LC16                       |ram:132|R_COUNT0
toplev@LC12                       |ram:132|R_COUNT1
toplev@LC10                       |ram:132|R_COUNT2
toplev@LC14                       |ram:132|R_COUNT3
toplev@LC5                        |ram:132|R_COUNT4
toplev@LC8                        |ram:132|R_COUNT5
toplev@LC116                      |ram:132|R_COUNT6
toplev@LC123                      |ram:132|R_COUNT7
toplev@LC3                        |ram:132|R_COUNT8
toplev@50                         /RAS
toplev@1                          /RESET
toplev@LC105                      |rom:154.ao0
toplev@LC81                       |rom:154.ao1
toplev@LC71                       |rom:154.ao2
toplev@LC66                       |rom:154.ao3
toplev@LC67                       |rom:154|COUNTER4
toplev@LC78                       |rom:154|rom_state~1
toplev@LC74                       |rom:154|rom_state~2
toplev@LC79                       |rom:154|rom_state~3
toplev@LC110                      |rom:154|rom_state~4
toplev@21                         Speed_Select_0
toplev@44                         /TA
toplev@16                         /TBST
toplev@6                          /TS
toplev@20                         TSIZ0
toplev@22                         TSIZ1
toplev@4                          TSIZ2
toplev@15                         TT1
toplev@55                         /we_ram
toplev@71                         XR
toplev@2                          2xPCLK
toplev@LC108                      :126
toplev@LC111                      :181
toplev@LC102                      :182
toplev@LC33                       :184


Project Information                                         c:\bean\toplev.rpt

** STATE MACHINE ASSIGNMENTS **


|abus:127.addr_st: MACHINE
        OF BITS (
           |abus:127|addr_state~3,
           |abus:127|addr_state~2,
           |abus:127|addr_state~1
        )
        WITH STATES (
                       ADDR_IDLE = B"000", 
                      ADDR_LATCH = B"010", 
                    ADDR_LATCHED = B"001", 
                     ADDR_BACKUP = B"101", 
                     ADDR_OPENUP = B"011", 
                         ADDR_X1 = B"111", 
                         ADDR_X2 = B"110", 
                         ADDR_X3 = B"100"
);


|dbus:129.data_st: MACHINE
        OF BITS (
           |dbus:129|data_state~2,
           |dbus:129|data_state~1
        )
        WITH STATES (
                       DATA_IDLE = B"00", 
                         DATA_GO = B"10", 
                       DATA_WAIT = B"11", 
                         DATA_TA = B"01"
);


|ram:132|ram_state: MACHINE
        OF BITS (
           |ram:132|ram_state~4,
           |ram:132|ram_state~3,
           |ram:132|ram_state~2,
           |ram:132|ram_state~1
        )
        WITH STATES (
                        RAM_IDLE = B"0000", 
                         RAM_CAS = B"1011", 
                         RAM_RAS = B"1000", 
                       RAM_WAIT1 = B"1001", 
                       RAM_WAIT2 = B"1010", 
                       RAM_WAIT3 = B"0011", 
                        RAM_RET1 = B"0010", 
                        RAM_RET2 = B"0001", 
                     RAM_COUNTER = B"1101", 
                      RAM_COUNT1 = B"0111", 
                      RAM_COUNT2 = B"0100", 
                      RAM_COUNT3 = B"0101", 
                      RAM_COUNT4 = B"0110", 
                     RAM_RASHOLD = B"1100", 
                          RAM_X1 = B"1111", 
                          RAM_X2 = B"1110"
);


|rom:154|rom_state: MACHINE
        OF BITS (
           |rom:154|rom_state~4,
           |rom:154|rom_state~3,
           |rom:154|rom_state~2,
           |rom:154|rom_state~1
        )
        WITH STATES (
                        ROM_IDLE = B"0000", 
                       ROM_COUNT = B"1000", 
                      ROM_TCOUNT = B"1010", 
                        ROM_WAIT = B"0101", 
                       ROM_WAIT2 = B"0110", 
                       ROM_WAIT3 = B"0111", 
                       ROM_WAIT4 = B"0010", 
                       ROM_LATCH = B"0011", 
                        ROM_INCR = B"0100", 
                      ROM_LASTTA = B"0001", 
                          ROM_X1 = B"1001", 
                          ROM_X2 = B"1011", 
                          ROM_X3 = B"1101", 
                          ROM_X4 = B"1111", 
                          ROM_X5 = B"1100", 
                          ROM_X6 = B"1110"
);


|io:162|io_state: MACHINE
        OF BITS (
           |io:162|io_state~3,
           |io:162|io_state~2,
           |io:162|io_state~1
        )
        WITH STATES (
                         IO_IDLE = B"000", 
                           IO_EH = B"001", 
                           IO_EL = B"101", 
                       IO_CSHOLD = B"011", 
                           IO_CS = B"100", 
                        IO_EWAIT = B"110", 
                       IO_EWAIT2 = B"010", 
                           IO_X1 = B"111"
);


|io:162|E_clock: MACHINE
        OF BITS (
           |io:162|E_clock~3,
           |io:162|E_clock~2,
           |io:162|E_clock~1
        )
        WITH STATES (
                             E_0 = B"000", 
                             E_1 = B"110", 
                             E_2 = B"101", 
                             E_3 = B"100", 
                             E_4 = B"011", 
                             E_5 = B"010", 
                             E_6 = B"001", 
                             E_7 = B"111"
);


|io:162|XR_clock: MACHINE
        OF BITS (
           |io:162|XR_clock~3,
           |io:162|XR_clock~2,
           |io:162|XR_clock~1
        )
        WITH STATES (
                            XR_0 = B"000", 
                            XR_1 = B"101", 
                            XR_2 = B"100", 
                            XR_3 = B"011", 
                            XR_4 = B"010", 
                            XR_5 = B"001", 
                            XR_6 = B"111", 
                            XR_7 = B"110"
);



Project Information                                         c:\bean\toplev.rpt

** FILE HIERARCHY **



|abus:127|
|dbus:129|
|ram:132|
|rom:154|
|io:162|
|busmux:175|
|busmux:175|lpm_mux:43|
|busmux:175|lpm_mux:43|altshift:external_latency_ffs|
|busmux:175|lpm_mux:43|muxlut:60|
|busmux:175|lpm_mux:43|muxlut:73|
|busmux:175|lpm_mux:43|muxlut:86|
|busmux:175|lpm_mux:43|muxlut:99|
|busmux:175|lpm_mux:43|muxlut:112|
|3mux:177|
|8and:200|
|addr3mux:207|


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

***** Logic for device 'toplev' compiled without errors.




Device: EPM7128ELC84-10
Turbo: ON
Security: OFF


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** ERROR SUMMARY **

Info: Chip 'toplev' in device 'EPM7128ELC84-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                                                                   
                                                                                   
                                                                                   
                                                                                   
                                                                                /  
                    A                                                           C  
                    d  A  A  A        R                          R  /     R  A  S  
                    d  d  d  d        E                       A  E  C     E  C  _  
                    r  d  d  d        S        2  /           C  S  S     S  I  R  
                    _  r  r  r        E  T     x  R           I  E  _     E  A  A  
                    I  _  _  _        R  S     P  E     P     A  R  R     R  _  M  
                    n  I  I  I  G  /  V  I  V  C  S  G  C  G  /  V  O  V  V  R  I  
                    _  n  n  n  N  T  E  Z  C  L  E  N  L  N  C  E  M  C  E  /  O  
                    o  1  0  4  D  S  D  2  C  K  T  D  K  D  S  D  2  C  D  W  2  
                  -----------------------------------------------------------------_ 
                /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
     Addr_In_z | 12                                                              74 | /CS_RAMIO1 
           VCC | 13                                                              73 | ACIA_RS 
        LTT1_2 | 14                                                              72 | GND 
           TT1 | 15                                                              71 | XR 
         /TBST | 16                                                              70 | RESERVED 
      Addr_In2 | 17                                                              69 | BYTE_LANE3 
       E_CLOCK | 18                                                              68 | RESERVED 
           GND | 19                                                              67 | BYTE_LANE2 
         TSIZ0 | 20                                                              66 | VCC 
Speed_Select_0 | 21                                                              65 | BYTE_LANE1 
         TSIZ1 | 22                       EPM7128ELC84-10                        64 | BYTE_LANE0 
     Addr_Out0 | 23                                                              63 | RESERVED 
        /CS_IO | 24                                                              62 | Addr_Out1 
    Addr_Latch | 25                                                              61 | RESERVED 
           VCC | 26                                                              60 | BYTE_LANE7 
         /AACK | 27                                                              59 | GND 
       /CS_ROM | 28                                                              58 | BYTE_LANE5 
         /CAS0 | 29                                                              57 | BYTE_LANE6 
          LTT1 | 30                                                              56 | RESERVED 
     Addr_Out2 | 31                                                              55 | /we_ram 
           GND | 32                                                              54 | BYTE_LANE4 
               |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
                 ------------------------------------------------------------------ 
                    /  /  /  R  /  V  /  /  /  G  V  /  R  A  G  C  A  /  R  A  V  
                    C  C  C  E  C  C  C  C  C  N  C  T  E  d  N  /  d  R  E  d  C  
                    A  A  A  S  A  C  A  A  A  D  C  A  S  d  D  R  d  A  S  d  C  
                    S  S  S  E  S     S  S  S           E  r     _  r  S  E  r     
                    4  2  5  R  6     3  7  1           R  _     M  _     R  _     
                             V                          V  I     U  O     V  O     
                             E                          E  n     X  u     E  u     
                             D                          D  3        t     D  t     
                                                                    4        3     
                                                                                   
                                                                                   
                                                                                   
                                                                                   
                                                                                   


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    12/16( 75%)   7/ 8( 87%)   2/16( 12%)  31/36( 86%) 
B:    LC17 - LC32    15/16( 93%)   8/ 8(100%)   3/16( 18%)  32/36( 88%) 
C:    LC33 - LC48    15/16( 93%)   8/ 8(100%)   0/16(  0%)  21/36( 58%) 
D:    LC49 - LC64    16/16(100%)   7/ 8( 87%)  11/16( 68%)   9/36( 25%) 
E:    LC65 - LC80    14/16( 87%)   6/ 8( 75%)   3/16( 18%)  32/36( 88%) 
F:    LC81 - LC96    13/16( 81%)   6/ 8( 75%)   5/16( 31%)  28/36( 77%) 
G:   LC97 - LC112    16/16(100%)   5/ 8( 62%)   4/16( 25%)  33/36( 91%) 
H:  LC113 - LC128    11/16( 68%)   6/ 8( 75%)   3/16( 18%)  28/36( 77%) 


Total dedicated input pins used:                 3/4    ( 75%)
Total I/O pins used:                            53/64   ( 82%)
Total logic cells used:                        112/128  ( 87%)
Total shareable expanders used:                  0/128  (  0%)
Total Turbo logic cells used:                  112/128  ( 87%)
Total shareable expanders not available (n/a):  31/128  ( 24%)

Total input pins required:                      17
Total input registers required:                  0
Total output pins required:                     39
Total bidirectional pins required:               0
Total logic cells required:                    112
Total flipflops required:                       52
Total shareable expanders in database:           0

Synthesized logic cells:                         4/ 128 (  3%)



Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  11    (5)  (A)      INPUT              0      0   0    0    0   18    7  Addr_In_o
  12    (3)  (A)      INPUT              0      0   0    0    0   18   10  Addr_In_z
   9    (8)  (A)      INPUT              0      0   0    0    0    9    1  Addr_In0
  10    (6)  (A)      INPUT              0      0   0    0    0    9    1  Addr_In1
  17   (25)  (B)      INPUT              0      0   0    0    0    9    0  Addr_In2
  46   (69)  (E)      INPUT              0      0   0    0    0    2    0  Addr_In3
   8   (11)  (A)      INPUT              0      0   0    0    0    1    0  Addr_In4
  83      -   -       INPUT              0      0   0    0    0    0    0  PCLK
   1      -   -       INPUT              0      0   0    0    0    1    0  /RESET
  21   (19)  (B)      INPUT              0      0   0    0    0    0    6  Speed_Select_0
  16   (27)  (B)      INPUT              0      0   0    0    0    0    1  /TBST
   6   (13)  (A)      INPUT              0      0   0    0    0    0    3  /TS
  20   (21)  (B)      INPUT              0      0   0    0    0    0    1  TSIZ0
  22   (17)  (B)      INPUT              0      0   0    0    0    0    1  TSIZ1
   4   (16)  (A)      INPUT              0      0   0    0    0    0    1  TSIZ2
  15   (29)  (B)      INPUT              0      0   0    0    0    2    0  TT1
   2      -   -       INPUT              0      0   0    0    0    0    0  2xPCLK


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  27     43    C     OUTPUT     t        0      0   0    0    3    0    0  /AACK
  81    128    H     OUTPUT     t        0      0   0    0    2    0    0  ACIA/CS
  73    115    H     OUTPUT     t        0      0   0    1    2    0    0  ACIA_RS
  76    120    H     OUTPUT     t        0      0   0    0    3    0    0  ACIA_R/W
  25     45    C     OUTPUT     t        0      0   0    0    3    0    0  Addr_Latch
  23     48    C     OUTPUT     t        0      0   0    3    1    0    0  Addr_Out0
  62     96    F     OUTPUT     t        0      0   0    3    1    0    0  Addr_Out1
  31     35    C     OUTPUT     t        0      0   0    3    1    0    0  Addr_Out2
  52     80    E     OUTPUT     t        0      0   0    3    3    0    0  Addr_Out3
  49     73    E     OUTPUT     t        0      0   0    3    2    0    0  Addr_Out4
  64     99    G     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE0
  65    101    G     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE1
  67    104    G     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE2
  69    107    G     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE3
  54     83    F     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE4
  58     91    F     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE5
  57     88    F     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE6
  60     93    F     OUTPUT     t        1      0   1    2   18    0    0  BYTE_LANE7
  29     38    C     OUTPUT     t        0      0   0    3    3    0    0  /CAS0
  41     49    D     OUTPUT     t        1      0   1    3    6    0    0  /CAS1
  34     61    D     OUTPUT     t        1      0   1    3    6    0    0  /CAS2
  39     53    D     OUTPUT     t        1      0   1    3    6    0    0  /CAS3
  33     64    D     OUTPUT     t        1      0   1    3    6    0    0  /CAS4
  35     59    D     OUTPUT     t        1      0   1    3    6    0    0  /CAS5
  37     56    D     OUTPUT     t        1      0   1    3    6    0    0  /CAS6
  40     51    D     OUTPUT     t        1      0   1    3    6    0    0  /CAS7
  48     72    E     OUTPUT     t        0      0   0    0    2    0    0  C/R_MUX
  24     46    C     OUTPUT     t        0      0   0    2    0    0    0  /CS_IO
  74    117    H     OUTPUT     t        0      0   0    2    0    0    0  /CS_RAMIO1
  75    118    H     OUTPUT     t        0      0   0    2    0    0    0  /CS_RAMIO2
  28     40    C     OUTPUT     t        0      0   0    2    1    0    0  /CS_ROM
  79    125    H     OUTPUT     t        0      0   0    2    1    0    0  /CS_ROM2
  18     24    B         FF  +  t        0      0   0    0    3    1    6  E_CLOCK (|io:162|E_FF)
  14     32    B         FF     t        0      0   0    1    3   12    2  LTT1_2
  30     37    C         FF     t        0      0   0    1    3    0    0  LTT1
  50     75    E         FF  +  t !      1      0   1    1    4    0    0  /RAS
  44     65    E     OUTPUT     t        1      0   1    0    2    0    0  /TA
  55     85    F     OUTPUT     t        0      0   0    0    3    0    0  /we_ram
  71    112    G         FF     t        0      0   0    0    4    0    0  XR (|io:162|XR_FF)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     39    C       TFFE  +  t        0      0   0    1    4    4    8  |abus:127|addr_state~1
   -     36    C       DFFE  +  t        0      0   0    1    4    4    8  |abus:127|addr_state~2
   -     34    C       DFFE  +  t        0      0   0    1    4    4    8  |abus:127|addr_state~3
 (63)    97    G       TFFE  +  t        0      0   0    0    4    1   12  |dbus:129|data_state~1
 (70)   109    G       TFFE  +  t        0      0   0    0    7    1   12  |dbus:129|data_state~2
   -     20    B       TFFE  +  t        0      0   0    0    3    9    6  |io:162|E_clock~1
 (21)    19    B       TFFE  +  t        0      0   0    0    3    9    6  |io:162|E_clock~2
   -     23    B       TFFE  +  t        0      0   0    0    3    9    6  |io:162|E_clock~3
   -     95    F       DFFE  +s t  r     1      0   1    2    9    1    3  |io:162|io_state~1~fit~in1
 (46)    69    E       SOFT     t        0      0   0    0    1   10    5  |io:162|io_state~1
   -     68    E       DFFE  +  t        0      0   0    0    4    8    6  |io:162|io_state~2
 (51)    77    E       TFFE  +  t        0      0   0    2    7   11    6  |io:162|io_state~3
 (56)    86    F       TFFE     t        0      0   0    0    4    1    3  |io:162|XR_clock~1
   -     15    A       DFFE     t        0      0   0    0    4    1    3  |io:162|XR_clock~2
   -     28    B       DFFE     t        0      0   0    0    4    1    3  |io:162|XR_clock~3
 (16)    27    B       DFFE  +  t        0      0   0    0    6    1    4  |ram:132.ao3 (|ram:132|B_COUNT0)
   -     18    B       DFFE  +  t        0      0   0    0    7    1    3  |ram:132|B_COUNT1
 (22)    17    B       DFFE  +  t        0      0   0    0    4    8    0  |ram:132|CAS_FF
   -     22    B       DFFE  +  t        1      0   1    2   18    9   15  |ram:132|ram_state~1
   -     26    B       TFFE  +  t        1      0   1    0   13    9   15  |ram:132|ram_state~2
   -    127    H       DFFE  +s t  r     1      0   1    1   18    0    2  |ram:132|ram_state~3~fit~in1
   -     30    B       SOFT     t        0      0   0    0    1   11   14  |ram:132|ram_state~3
 (15)    29    B       TFFE  +  t        1      0   1    1   15   11   15  |ram:132|ram_state~4
  (4)    16    A       TFFE  +  t        0      0   0    1    9    0   14  |ram:132|R_COUNT0
   -     12    A       TFFE  +  t        0      0   0    0    1    0   13  |ram:132|R_COUNT1
   -     10    A       TFFE  +  t        0      0   0    0    2    0   12  |ram:132|R_COUNT2
  (5)    14    A       TFFE  +  t        0      0   0    0    3    0   11  |ram:132|R_COUNT3
 (11)     5    A       TFFE  +  t        0      0   0    1   13    0   11  |ram:132|R_COUNT4
  (9)     8    A       TFFE  +  t        0      0   0    0    5    0   10  |ram:132|R_COUNT5
   -    116    H       TFFE  +  t        0      0   0    1   13    0   10  |ram:132|R_COUNT6
 (77)   123    H       TFFE  +  t        0      0   0    1   13    0   10  |ram:132|R_COUNT7
 (12)     3    A       TFFE  +  t        0      0   0    1   13    0   10  |ram:132|R_COUNT8
   -    113    H       DFFE  +  t        1      0   1    0   14    8    2  |ram:132.ram_refresh (|ram:132|REFRESH)
 (68)   105    G       DFFE  +  t        0      0   0    0    5    9    8  |rom:154.ao0 (|rom:154|COUNTER0)
   -     81    F       TFFE  +  t        0      0   0    0    6    9    7  |rom:154.ao1 (|rom:154|COUNTER1)
   -     71    E       TFFE  +  t        0      0   0    0    7    9    6  |rom:154.ao2 (|rom:154|COUNTER2)
   -     66    E       TFFE  +  t        1      0   1    1    8    1    4  |rom:154.ao3 (|rom:154|COUNTER3)
   -      2    A       TFFE  +s t  r     1      0   1    1    9    0    2  |rom:154|COUNTER4~fit~in1
 (45)    67    E       SOFT     t        0      0   0    0    1    1    2  |rom:154|COUNTER4
   -     78    E       TFFE  +  t        0      0   0    0   10    8   12  |rom:154|rom_state~1
   -     74    E       DFFE  +  t        0      0   0    2    8    8   11  |rom:154|rom_state~2
   -      7    A       DFFE  +s t  r     1      0   1    0   10    0    2  |rom:154|rom_state~3~fit~in1
   -     79    E       SOFT     t        0      0   0    0    1    8   11  |rom:154|rom_state~3
   -    110    G       DFFE  +  t        0      0   0    2    7    8   12  |rom:154|rom_state~4
   -    108    G       TFFE  +  t        0      0   0    2   13    0    2  :126
   -    111    G       TFFE  +  t        0      0   0    2   20    0    2  :181
   -    102    G       TFFE  +  t        0      0   0    2   18    0    6  :182
   -     33    C       DFFE     t        0      0   0    1    3    9    7  :184
   -     41    C       DFFE     t        0      0   0    1    3    7    0  LTSIZ0 (~196~1)
   -     42    C       DFFE     t        0      0   0    1    3    7    0  LTSIZ1 (~196~2)
   -     44    C       DFFE     t        0      0   0    1    3    7    0  LTSIZ2 (~196~3)
   -     98    G       PEXP     t        0      0   0    0    0    0    0  _LC098
   -    100    G       PEXP     t        0      0   0    0    0    0    0  _LC100
   -    103    G       PEXP     t        0      0   0    0    0    0    0  _LC103
   -    106    G       PEXP     t        0      0   0    0    0    0    0  _LC106
   -     82    F       PEXP     t        0      0   0    0    0    0    0  _LC082
   -     90    F       PEXP     t        0      0   0    0    0    0    0  _LC090
   -     87    F       PEXP     t        0      0   0    0    0    0    0  _LC087
   -     92    F       PEXP     t        0      0   0    0    0    0    0  _LC092
   -     60    D       PEXP     t        0      0   0    0    0    0    0  _LC060
   -     52    D       PEXP     t        0      0   0    0    0    0    0  _LC052
   -     63    D       PEXP     t        1      0   1    0    0    0    0  _LC063
   -     62    D       PEXP     t        0      0   0    0    0    0    0  _LC062
   -     58    D       PEXP     t        1      0   1    0    0    0    0  _LC058
 (36)    57    D       PEXP     t        0      0   0    0    0    0    0  _LC057
   -     55    D       PEXP     t        1      0   1    0    0    0    0  _LC055
   -     54    D       PEXP     t        0      0   0    0    0    0    0  _LC054
   -     50    D       PEXP     t        1      0   1    0    0    0    0  _LC050
 (20)    21    B       PEXP     t        0      0   0    0    0    0    0  _LC021
 (17)    25    B       PEXP     t        0      0   0    0    0    0    0  _LC025
 (80)   126    H       PEXP     t        1      0   1    0    0    0    0  _LC126
   -      1    A       PEXP     t        0      0   0    0    0    0    0  _LC001
 (10)     6    A       PEXP     t        0      0   0    0    0    0    0  _LC006


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                 Logic cells placed in LAB 'A'
        +----------------------- LC15 |io:162|XR_clock~2
        | +--------------------- LC16 |ram:132|R_COUNT0
        | | +------------------- LC12 |ram:132|R_COUNT1
        | | | +----------------- LC10 |ram:132|R_COUNT2
        | | | | +--------------- LC14 |ram:132|R_COUNT3
        | | | | | +------------- LC5 |ram:132|R_COUNT4
        | | | | | | +----------- LC8 |ram:132|R_COUNT5
        | | | | | | | +--------- LC3 |ram:132|R_COUNT8
        | | | | | | | | +------- LC2 |rom:154|COUNTER4~fit~in1
        | | | | | | | | | +----- LC7 |rom:154|rom_state~3~fit~in1
        | | | | | | | | | | +--- LC1 
        | | | | | | | | | | | +- LC6 
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'A':
LC15 -> * - - - - - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~2
LC16 -> - * * * * * * * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT0
LC12 -> - * * * * * * * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT1
LC10 -> - * - * * * * * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT2
LC14 -> - * - - * * * * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT3
LC5  -> - * - - - * * * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT4
LC8  -> - * - - - * * * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT5
LC3  -> - * - - - * - * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT8
LC2  -> - - - - - - - - * - - - | * - - - * - - - | <-- |rom:154|COUNTER4~fit~in1
LC7  -> - - - - - - - - - * - - | * - - - * - - - | <-- |rom:154|rom_state~3~fit~in1

Pin
10   -> - - - - - - - - * - - - | * - * * - * - - | <-- Addr_In1
83   -> - - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - - - - - - - | - - - - * - - - | <-- /RESET
21   -> - * - - - * - * - - - - | * * - - - - - * | <-- Speed_Select_0
2    -> - - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC24 -> * - - - - - - - - - - - | * * - - * * * - | <-- E_CLOCK
LC86 -> * - - - - - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~1
LC28 -> * - - - - - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~3
LC22 -> - - - - - * - * - - - - | * * - - * * * * | <-- |ram:132|ram_state~1
LC26 -> - - - - - * - * - - - - | * * - - * * * * | <-- |ram:132|ram_state~2
LC30 -> - - - - - * - * - - - - | * * - - * * * * | <-- |ram:132|ram_state~3
LC29 -> - - - - - * - * - - - - | * * - - * * * * | <-- |ram:132|ram_state~4
LC116-> - * - - - * - * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT6
LC123-> - * - - - * - * - - - - | * * - - - - - * | <-- |ram:132|R_COUNT7
LC105-> - - - - - - - - * * - - | * - * - * * * - | <-- |rom:154.ao0
LC81 -> - - - - - - - - * * - - | * - - - * * * - | <-- |rom:154.ao1
LC71 -> - - - - - - - - * * - - | * - * - * * * - | <-- |rom:154.ao2
LC66 -> - - - - - - - - * * - - | * - - - * - - - | <-- |rom:154.ao3
LC67 -> - - - - - - - - - * - - | * - - - * - - - | <-- |rom:154|COUNTER4
LC78 -> - - - - - - - - * * - - | * - - - * * * - | <-- |rom:154|rom_state~1
LC74 -> - - - - - - - - * * - - | * - - - * * * - | <-- |rom:154|rom_state~2
LC79 -> - - - - - - - - * - - - | * - - - * * * - | <-- |rom:154|rom_state~3
LC110-> - - - - - - - - * * - - | * - - - * * * - | <-- |rom:154|rom_state~4
LC33 -> - - - - - - - - - * - - | * * * * * - - * | <-- :184


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                       Logic cells placed in LAB 'B'
        +----------------------------- LC24 E_CLOCK
        | +--------------------------- LC20 |io:162|E_clock~1
        | | +------------------------- LC19 |io:162|E_clock~2
        | | | +----------------------- LC23 |io:162|E_clock~3
        | | | | +--------------------- LC28 |io:162|XR_clock~3
        | | | | | +------------------- LC32 LTT1_2
        | | | | | | +----------------- LC27 |ram:132.ao3
        | | | | | | | +--------------- LC18 |ram:132|B_COUNT1
        | | | | | | | | +------------- LC17 |ram:132|CAS_FF
        | | | | | | | | | +----------- LC22 |ram:132|ram_state~1
        | | | | | | | | | | +--------- LC26 |ram:132|ram_state~2
        | | | | | | | | | | | +------- LC30 |ram:132|ram_state~3
        | | | | | | | | | | | | +----- LC29 |ram:132|ram_state~4
        | | | | | | | | | | | | | +--- LC21 
        | | | | | | | | | | | | | | +- LC25 
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'B':
LC24 -> * - - - * - - - - - - - - - - | * * - - * * * - | <-- E_CLOCK
LC20 -> * * * * - - - - - - - - - - - | - * - - - * * - | <-- |io:162|E_clock~1
LC19 -> * * * * - - - - - - - - - - - | - * - - - * * - | <-- |io:162|E_clock~2
LC23 -> * * * * - - - - - - - - - - - | - * - - - * * - | <-- |io:162|E_clock~3
LC28 -> - - - - * - - - - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~3
LC27 -> - - - - - - * * - * - - - - - | - * - - * - - * | <-- |ram:132.ao3
LC18 -> - - - - - - - * - * - - - - - | - * - - * - - * | <-- |ram:132|B_COUNT1
LC22 -> - - - - - - * * * * * - * - - | * * - - * * * * | <-- |ram:132|ram_state~1
LC26 -> - - - - - - * * * * * - * - - | * * - - * * * * | <-- |ram:132|ram_state~2
LC30 -> - - - - - - * * * * * - * - - | * * - - * * * * | <-- |ram:132|ram_state~3
LC29 -> - - - - - - * * * * * - * - - | * * - - * * * * | <-- |ram:132|ram_state~4

Pin
12   -> - - - - - - - - - * - - * - - | - * * - * * * * | <-- Addr_In_z
83   -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - - - - - - - - - - | - - - - * - - - | <-- /RESET
21   -> - - - - - - - - - * - - - - - | * * - - - - - * | <-- Speed_Select_0
15   -> - - - - - * - - - - - - - - - | - * * - - - - - | <-- TT1
2    -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC39 -> - - - - - * - - - - - - - - - | - * * - - - * - | <-- |abus:127|addr_state~1
LC36 -> - - - - - * - - - - - - - - - | - * * - - - * - | <-- |abus:127|addr_state~2
LC34 -> - - - - - * - - - - - - - - - | - * * - - - * - | <-- |abus:127|addr_state~3
LC97 -> - - - - - - - - - * - - * - - | - * - - * * * * | <-- |dbus:129|data_state~1
LC109-> - - - - - - - - - * - - * - - | - * - - * * * * | <-- |dbus:129|data_state~2
LC86 -> - - - - * - - - - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~1
LC15 -> - - - - * - - - - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~2
LC127-> - - - - - - - - - - - * - - - | - * - - - - - * | <-- |ram:132|ram_state~3~fit~in1
LC16 -> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT0
LC12 -> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT1
LC10 -> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT2
LC14 -> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT3
LC5  -> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT4
LC8  -> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT5
LC116-> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT6
LC123-> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT7
LC3  -> - - - - - - - - - * * - * - - | * * - - - - - * | <-- |ram:132|R_COUNT8
LC33 -> - - - - - - * * - * - - - - - | * * * * * - - * | <-- :184


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                       Logic cells placed in LAB 'C'
        +----------------------------- LC43 /AACK
        | +--------------------------- LC39 |abus:127|addr_state~1
        | | +------------------------- LC36 |abus:127|addr_state~2
        | | | +----------------------- LC34 |abus:127|addr_state~3
        | | | | +--------------------- LC45 Addr_Latch
        | | | | | +------------------- LC48 Addr_Out0
        | | | | | | +----------------- LC35 Addr_Out2
        | | | | | | | +--------------- LC38 /CAS0
        | | | | | | | | +------------- LC46 /CS_IO
        | | | | | | | | | +----------- LC40 /CS_ROM
        | | | | | | | | | | +--------- LC37 LTT1
        | | | | | | | | | | | +------- LC33 :184
        | | | | | | | | | | | | +----- LC41 LTSIZ0
        | | | | | | | | | | | | | +--- LC42 LTSIZ1
        | | | | | | | | | | | | | | +- LC44 LTSIZ2
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'C':
LC39 -> * * * * * - - - - - * * * * * | - * * - - - * - | <-- |abus:127|addr_state~1
LC36 -> * * * * * - - - - - * * * * * | - * * - - - * - | <-- |abus:127|addr_state~2
LC34 -> * * * * * - - - - - * * * * * | - * * - - - * - | <-- |abus:127|addr_state~3
LC33 -> - - - - - - - * - - - - - - - | * * * * * - - * | <-- :184

Pin
11   -> - - - - - * * - * * - - - - - | - - * - * * * * | <-- Addr_In_o
12   -> - - - - - * * - * * - - - - - | - * * - * * * * | <-- Addr_In_z
9    -> - - - - - * - * - - - - - - - | - - * * * - - - | <-- Addr_In0
10   -> - - - - - - - * - - - - - - - | * - * * - * - - | <-- Addr_In1
17   -> - - - - - - * * - - - - - - - | - - * * - - - - | <-- Addr_In2
83   -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - - - - - - - - - - | - - - - * - - - | <-- /RESET
16   -> - - - - - - - - - - - * - - - | - - * - - - - - | <-- /TBST
6    -> - * * * - - - - - - - - - - - | - - * - - - - - | <-- /TS
20   -> - - - - - - - - - - - - - - * | - - * - - - - - | <-- TSIZ0
22   -> - - - - - - - - - - - - - * - | - - * - - - - - | <-- TSIZ1
4    -> - - - - - - - - - - - - * - - | - - * - - - - - | <-- TSIZ2
15   -> - - - - - - - - - - * - - - - | - * * - - - - - | <-- TT1
2    -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC32 -> - - - - - - - - - * - - - - - | - - * - * * * * | <-- LTT1_2
LC17 -> - - - - - - - * - - - - - - - | - - * * - - - - | <-- |ram:132|CAS_FF
LC113-> - - - - - - - * - - - - - - - | - - * * - - * * | <-- |ram:132.ram_refresh
LC105-> - - - - - * - - - - - - - - - | * - * - * * * - | <-- |rom:154.ao0
LC71 -> - - - - - - * - - - - - - - - | * - * - * * * - | <-- |rom:154.ao2
LC102-> - * * * - - - - - - - - - - - | - - * - - - * - | <-- :182


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC49 /CAS1
        | +----------------------------- LC61 /CAS2
        | | +--------------------------- LC53 /CAS3
        | | | +------------------------- LC64 /CAS4
        | | | | +----------------------- LC59 /CAS5
        | | | | | +--------------------- LC56 /CAS6
        | | | | | | +------------------- LC51 /CAS7
        | | | | | | | +----------------- LC60 
        | | | | | | | | +--------------- LC52 
        | | | | | | | | | +------------- LC63 
        | | | | | | | | | | +----------- LC62 
        | | | | | | | | | | | +--------- LC58 
        | | | | | | | | | | | | +------- LC57 
        | | | | | | | | | | | | | +----- LC55 
        | | | | | | | | | | | | | | +--- LC54 
        | | | | | | | | | | | | | | | +- LC50 
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'D':

Pin
9    -> * * * * * * * - - - - - - - - - | - - * * * - - - | <-- Addr_In0
10   -> * * * * * * * - - - - - - - - - | * - * * - * - - | <-- Addr_In1
17   -> * * * * * * * - - - - - - - - - | - - * * - - - - | <-- Addr_In2
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - - - - - - - - - - - | - - - - * - - - | <-- /RESET
2    -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC17 -> * * * * * * * - - - - - - - - - | - - * * - - - - | <-- |ram:132|CAS_FF
LC113-> * * * * * * * - - - - - - - - - | - - * * - - * * | <-- |ram:132.ram_refresh
LC33 -> * * * * * * * - - - - - - - - - | * * * * * - - * | <-- :184
LC41 -> * * * * * * * - - - - - - - - - | - - - * - - - - | <-- LTSIZ0
LC42 -> * * * * * * * - - - - - - - - - | - - - * - - - - | <-- LTSIZ1
LC44 -> * * * * * * * - - - - - - - - - | - - - * - - - - | <-- LTSIZ2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                     Logic cells placed in LAB 'E'
        +--------------------------- LC80 Addr_Out3
        | +------------------------- LC73 Addr_Out4
        | | +----------------------- LC72 C/R_MUX
        | | | +--------------------- LC69 |io:162|io_state~1
        | | | | +------------------- LC68 |io:162|io_state~2
        | | | | | +----------------- LC77 |io:162|io_state~3
        | | | | | | +--------------- LC75 /RAS
        | | | | | | | +------------- LC71 |rom:154.ao2
        | | | | | | | | +----------- LC66 |rom:154.ao3
        | | | | | | | | | +--------- LC67 |rom:154|COUNTER4
        | | | | | | | | | | +------- LC78 |rom:154|rom_state~1
        | | | | | | | | | | | +----- LC74 |rom:154|rom_state~2
        | | | | | | | | | | | | +--- LC79 |rom:154|rom_state~3
        | | | | | | | | | | | | | +- LC65 /TA
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC69 -> - - - - * * - - - - - - - - | - - - - * * * * | <-- |io:162|io_state~1
LC68 -> - - - - * * - - - - - - - - | - - - - * * * - | <-- |io:162|io_state~2
LC77 -> - - - - * * - - - - - - - - | - - - - * * * * | <-- |io:162|io_state~3
LC71 -> - - - - - - - * * - * - - - | * - * - * * * - | <-- |rom:154.ao2
LC66 -> * - - - - - - - * - * - - - | * - - - * - - - | <-- |rom:154.ao3
LC67 -> - * - - - - - - - - * - - - | * - - - * - - - | <-- |rom:154|COUNTER4
LC78 -> - - - - - - - * * - * * - - | * - - - * * * - | <-- |rom:154|rom_state~1
LC74 -> - - - - - - - * * - * * - - | * - - - * * * - | <-- |rom:154|rom_state~2
LC79 -> - - - - - - - * * - * * - - | * - - - * * * - | <-- |rom:154|rom_state~3

Pin
11   -> * * - - - * - - - - - * - - | - - * - * * * * | <-- Addr_In_o
12   -> * * - - - * - - - - - * - - | - * * - * * * * | <-- Addr_In_z
9    -> - - - - - - - - * - - - - - | - - * * * - - - | <-- Addr_In0
46   -> * - - - - - - - - - - - - - | - - - - * - - * | <-- Addr_In3
8    -> - * - - - - - - - - - - - - | - - - - * - - - | <-- Addr_In4
83   -> - - - - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - * - - - - - - - | - - - - * - - - | <-- /RESET
2    -> - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC97 -> - - - - - * - - - - - * - * | - * - - * * * * | <-- |dbus:129|data_state~1
LC109-> - - - - - * - - - - - * - * | - * - - * * * * | <-- |dbus:129|data_state~2
LC24 -> - - - - * * - - - - - - - - | * * - - * * * - | <-- E_CLOCK
LC95 -> - - - * - * - - - - - - - - | - - - - * * - * | <-- |io:162|io_state~1~fit~in1
LC32 -> - - - - - - - - - - - * - - | - - * - * * * * | <-- LTT1_2
LC27 -> * - - - - - - - - - - - - - | - * - - * - - * | <-- |ram:132.ao3
LC18 -> - * - - - - - - - - - - - - | - * - - * - - * | <-- |ram:132|B_COUNT1
LC22 -> - - - - - - * - - - - - - - | * * - - * * * * | <-- |ram:132|ram_state~1
LC26 -> - - - - - - * - - - - - - - | * * - - * * * * | <-- |ram:132|ram_state~2
LC30 -> - - * - - - * - - - - - - - | * * - - * * * * | <-- |ram:132|ram_state~3
LC29 -> - - * - - - * - - - - - - - | * * - - * * * * | <-- |ram:132|ram_state~4
LC105-> - - - - - - - * * - * - - - | * - * - * * * - | <-- |rom:154.ao0
LC81 -> - - - - - - - * * - * - - - | * - - - * * * - | <-- |rom:154.ao1
LC2  -> - - - - - - - - - * - - - - | * - - - * - - - | <-- |rom:154|COUNTER4~fit~in1
LC7  -> - - - - - - - - - - - - * - | * - - - * - - - | <-- |rom:154|rom_state~3~fit~in1
LC110-> - - - - - - - * * - * * - - | * - - - * * * - | <-- |rom:154|rom_state~4
LC33 -> * - - - - - - - - - * * - - | * * * * * - - * | <-- :184


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                   Logic cells placed in LAB 'F'
        +------------------------- LC96 Addr_Out1
        | +----------------------- LC83 BYTE_LANE4
        | | +--------------------- LC91 BYTE_LANE5
        | | | +------------------- LC88 BYTE_LANE6
        | | | | +----------------- LC93 BYTE_LANE7
        | | | | | +--------------- LC95 |io:162|io_state~1~fit~in1
        | | | | | | +------------- LC86 |io:162|XR_clock~1
        | | | | | | | +----------- LC81 |rom:154.ao1
        | | | | | | | | +--------- LC85 /we_ram
        | | | | | | | | | +------- LC82 
        | | | | | | | | | | +----- LC90 
        | | | | | | | | | | | +--- LC87 
        | | | | | | | | | | | | +- LC92 
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC95 -> - - - - - * - - - - - - - | - - - - * * - * | <-- |io:162|io_state~1~fit~in1
LC86 -> - - - - - - * - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~1
LC81 -> * * * * * - - * - - - - - | * - - - * * * - | <-- |rom:154.ao1

Pin
11   -> * * * * * * - - - - - - - | - - * - * * * * | <-- Addr_In_o
12   -> * * * * * * - - - - - - - | - * * - * * * * | <-- Addr_In_z
10   -> * - - - - - - - - - - - - | * - * * - * - - | <-- Addr_In1
83   -> - - - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - - - - - - - - | - - - - * - - - | <-- /RESET
2    -> - - - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC97 -> - - - - - * - - - - - - - | - * - - * * * * | <-- |dbus:129|data_state~1
LC109-> - - - - - * - - - - - - - | - * - - * * * * | <-- |dbus:129|data_state~2
LC24 -> - - - - - * * - - - - - - | * * - - * * * - | <-- E_CLOCK
LC20 -> - * * * * * - - - - - - - | - * - - - * * - | <-- |io:162|E_clock~1
LC19 -> - * * * * * - - - - - - - | - * - - - * * - | <-- |io:162|E_clock~2
LC23 -> - * * * * * - - - - - - - | - * - - - * * - | <-- |io:162|E_clock~3
LC69 -> - * * * * - - - - - - - - | - - - - * * * * | <-- |io:162|io_state~1
LC68 -> - * * * * * - - - - - - - | - - - - * * * - | <-- |io:162|io_state~2
LC77 -> - * * * * * - - - - - - - | - - - - * * * * | <-- |io:162|io_state~3
LC15 -> - - - - - - * - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~2
LC28 -> - - - - - - * - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~3
LC32 -> - * * * * - - - * - - - - | - - * - * * * * | <-- LTT1_2
LC22 -> - * * * * - - - - - - - - | * * - - * * * * | <-- |ram:132|ram_state~1
LC26 -> - * * * * - - - - - - - - | * * - - * * * * | <-- |ram:132|ram_state~2
LC30 -> - * * * * - - - * - - - - | * * - - * * * * | <-- |ram:132|ram_state~3
LC29 -> - * * * * - - - * - - - - | * * - - * * * * | <-- |ram:132|ram_state~4
LC105-> - * * * * - - * - - - - - | * - * - * * * - | <-- |rom:154.ao0
LC71 -> - * * * * - - - - - - - - | * - * - * * * - | <-- |rom:154.ao2
LC78 -> - * * * * - - * - - - - - | * - - - * * * - | <-- |rom:154|rom_state~1
LC74 -> - * * * * - - * - - - - - | * - - - * * * - | <-- |rom:154|rom_state~2
LC79 -> - * * * * - - * - - - - - | * - - - * * * - | <-- |rom:154|rom_state~3
LC110-> - * * * * - - * - - - - - | * - - - * * * - | <-- |rom:154|rom_state~4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                         Logic cells placed in LAB 'G'
        +------------------------------- LC99 BYTE_LANE0
        | +----------------------------- LC101 BYTE_LANE1
        | | +--------------------------- LC104 BYTE_LANE2
        | | | +------------------------- LC107 BYTE_LANE3
        | | | | +----------------------- LC97 |dbus:129|data_state~1
        | | | | | +--------------------- LC109 |dbus:129|data_state~2
        | | | | | | +------------------- LC105 |rom:154.ao0
        | | | | | | | +----------------- LC110 |rom:154|rom_state~4
        | | | | | | | | +--------------- LC112 XR
        | | | | | | | | | +------------- LC108 :126
        | | | | | | | | | | +----------- LC111 :181
        | | | | | | | | | | | +--------- LC102 :182
        | | | | | | | | | | | | +------- LC98 
        | | | | | | | | | | | | | +----- LC100 
        | | | | | | | | | | | | | | +--- LC103 
        | | | | | | | | | | | | | | | +- LC106 
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC97 -> - - - - * * - * - * * * - - - - | - * - - * * * * | <-- |dbus:129|data_state~1
LC109-> - - - - * * - * - * * * - - - - | - * - - * * * * | <-- |dbus:129|data_state~2
LC105-> * * * * - - * - - - * - - - - - | * - * - * * * - | <-- |rom:154.ao0
LC110-> * * * * - - * * - * * * - - - - | * - - - * * * - | <-- |rom:154|rom_state~4
LC108-> - - - - * - - - - * - - - - - - | - - - - - - * - | <-- :126
LC111-> - - - - - * - - - - * - - - - - | - - - - - - * - | <-- :181
LC102-> - - - - * * - - - - - * - - - - | - - * - - - * - | <-- :182

Pin
11   -> * * * * - - - * - * * * - - - - | - - * - * * * * | <-- Addr_In_o
12   -> * * * * - - - * - * * * - - - - | - * * - * * * * | <-- Addr_In_z
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - - - - - - - - - - - | - - - - * - - - | <-- /RESET
2    -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC39 -> - - - - - * - - - - - - - - - - | - * * - - - * - | <-- |abus:127|addr_state~1
LC36 -> - - - - - * - - - - - - - - - - | - * * - - - * - | <-- |abus:127|addr_state~2
LC34 -> - - - - - * - - - - - - - - - - | - * * - - - * - | <-- |abus:127|addr_state~3
LC24 -> - - - - - - - - * - - - - - - - | * * - - * * * - | <-- E_CLOCK
LC20 -> * * * * - - - - - - * * - - - - | - * - - - * * - | <-- |io:162|E_clock~1
LC19 -> * * * * - - - - - - * * - - - - | - * - - - * * - | <-- |io:162|E_clock~2
LC23 -> * * * * - - - - - - * * - - - - | - * - - - * * - | <-- |io:162|E_clock~3
LC69 -> * * * * - - - - - * * * - - - - | - - - - * * * * | <-- |io:162|io_state~1
LC68 -> * * * * - - - - - * * * - - - - | - - - - * * * - | <-- |io:162|io_state~2
LC77 -> * * * * - - - - - * * * - - - - | - - - - * * * * | <-- |io:162|io_state~3
LC86 -> - - - - - - - - * - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~1
LC15 -> - - - - - - - - * - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~2
LC28 -> - - - - - - - - * - - - - - - - | * * - - - * * - | <-- |io:162|XR_clock~3
LC32 -> * * * * - - - * - - - - - - - - | - - * - * * * * | <-- LTT1_2
LC22 -> * * * * - - - - - * * * - - - - | * * - - * * * * | <-- |ram:132|ram_state~1
LC26 -> * * * * - - - - - * * * - - - - | * * - - * * * * | <-- |ram:132|ram_state~2
LC30 -> * * * * - - - - - * * * - - - - | * * - - * * * * | <-- |ram:132|ram_state~3
LC29 -> * * * * - - - - - * * * - - - - | * * - - * * * * | <-- |ram:132|ram_state~4
LC113-> - - - - - - - - - - - * - - - - | - - * * - - * * | <-- |ram:132.ram_refresh
LC81 -> * * * * - - - - - - * - - - - - | * - - - * * * - | <-- |rom:154.ao1
LC71 -> * * * * - - - - - - * - - - - - | * - * - * * * - | <-- |rom:154.ao2
LC78 -> * * * * - - * * - * * * - - - - | * - - - * * * - | <-- |rom:154|rom_state~1
LC74 -> * * * * - - * * - - * * - - - - | * - - - * * * - | <-- |rom:154|rom_state~2
LC79 -> * * * * - - * * - * * * - - - - | * - - - * * * - | <-- |rom:154|rom_state~3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                               Logic cells placed in LAB 'H'
        +--------------------- LC128 ACIA/CS
        | +------------------- LC115 ACIA_RS
        | | +----------------- LC120 ACIA_R/W
        | | | +--------------- LC117 /CS_RAMIO1
        | | | | +------------- LC118 /CS_RAMIO2
        | | | | | +----------- LC125 /CS_ROM2
        | | | | | | +--------- LC127 |ram:132|ram_state~3~fit~in1
        | | | | | | | +------- LC116 |ram:132|R_COUNT6
        | | | | | | | | +----- LC123 |ram:132|R_COUNT7
        | | | | | | | | | +--- LC113 |ram:132.ram_refresh
        | | | | | | | | | | +- LC126 
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC127-> - - - - - - * - - - - | - * - - - - - * | <-- |ram:132|ram_state~3~fit~in1
LC116-> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT6
LC123-> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT7
LC113-> - - - - - - - - - * - | - - * * - - * * | <-- |ram:132.ram_refresh

Pin
11   -> - - - * * * - - - - - | - - * - * * * * | <-- Addr_In_o
12   -> - - - * * * * - - - - | - * * - * * * * | <-- Addr_In_z
46   -> - * - - - - - - - - - | - - - - * - - * | <-- Addr_In3
83   -> - - - - - - - - - - - | - - - - - - - - | <-- PCLK
1    -> - - - - - - - - - - - | - - - - * - - - | <-- /RESET
21   -> - - - - - - - * * - - | * * - - - - - * | <-- Speed_Select_0
2    -> - - - - - - - - - - - | - - - - - - - - | <-- 2xPCLK
LC97 -> - - - - - - * - - - - | - * - - * * * * | <-- |dbus:129|data_state~1
LC109-> - - - - - - * - - - - | - * - - * * * * | <-- |dbus:129|data_state~2
LC95 -> * - - - - - - - - - - | - - - - * * - * | <-- |io:162|io_state~1~fit~in1
LC69 -> - * * - - - - - - - - | - - - - * * * * | <-- |io:162|io_state~1
LC77 -> * * * - - - - - - - - | - - - - * * * * | <-- |io:162|io_state~3
LC32 -> - - * - - * - - - - - | - - * - * * * * | <-- LTT1_2
LC27 -> - - - - - - * - - - - | - * - - * - - * | <-- |ram:132.ao3
LC18 -> - - - - - - * - - - - | - * - - * - - * | <-- |ram:132|B_COUNT1
LC22 -> - - - - - - * * * * - | * * - - * * * * | <-- |ram:132|ram_state~1
LC26 -> - - - - - - * * * * - | * * - - * * * * | <-- |ram:132|ram_state~2
LC30 -> - - - - - - - * * * - | * * - - * * * * | <-- |ram:132|ram_state~3
LC29 -> - - - - - - * * * * - | * * - - * * * * | <-- |ram:132|ram_state~4
LC16 -> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT0
LC12 -> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT1
LC10 -> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT2
LC14 -> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT3
LC5  -> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT4
LC8  -> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT5
LC3  -> - - - - - - * * * * - | * * - - - - - * | <-- |ram:132|R_COUNT8
LC33 -> - - - - - - * - - - - | * * * * * - - * | <-- :184


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                c:\bean\toplev.rpt
toplev

** EQUATIONS **

Addr_In_o : INPUT;
Addr_In_z : INPUT;
Addr_In0 : INPUT;
Addr_In1 : INPUT;
Addr_In2 : INPUT;
Addr_In3 : INPUT;
Addr_In4 : INPUT;
PCLK     : INPUT;
Speed_Select_0 : INPUT;
TSIZ0    : INPUT;
TSIZ1    : INPUT;
TSIZ2    : INPUT;
TT1      : INPUT;
2xPCLK   : INPUT;
/RESET   : INPUT;
/TBST    : INPUT;
/TS      : INPUT;

-- Node name is 'ACIA/CS' 
-- Equation name is 'ACIA/CS', location is LC128, type is output.
 ACIA/CS = LCELL( _EQ001 $  VCC);
  _EQ001 =  _LC077 & !_LC095;

-- Node name is 'ACIA_RS' 
-- Equation name is 'ACIA_RS', location is LC115, type is output.
 ACIA_RS = LCELL( _EQ002 $  GND);
  _EQ002 =  Addr_In3 & !_LC069 &  _LC077;

-- Node name is 'ACIA_R/W' 
-- Equation name is 'ACIA_R/W', location is LC120, type is output.
 ACIA_R/W = LCELL( _EQ003 $  GND);
  _EQ003 = !_LC069 &  _LC077 &  LTT1_2;

-- Node name is 'Addr_Latch' 
-- Equation name is 'Addr_Latch', location is LC045, type is output.
 Addr_Latch = LCELL( _EQ004 $  GND);
  _EQ004 = !_LC034 &  _LC036 & !_LC039;

-- Node name is 'Addr_Out0' 
-- Equation name is 'Addr_Out0', location is LC048, type is output.
 Addr_Out0 = LCELL( _EQ005 $  Addr_In0);
  _EQ005 =  Addr_In_o &  Addr_In_z & !Addr_In0 &  _LC105
         #  Addr_In_o &  Addr_In_z &  Addr_In0 & !_LC105;

-- Node name is 'Addr_Out1' 
-- Equation name is 'Addr_Out1', location is LC096, type is output.
 Addr_Out1 = LCELL( _EQ006 $  Addr_In1);
  _EQ006 =  Addr_In_o &  Addr_In_z & !Addr_In1 &  _LC081
         #  Addr_In_o &  Addr_In_z &  Addr_In1 & !_LC081;

-- Node name is 'Addr_Out2' 
-- Equation name is 'Addr_Out2', location is LC035, type is output.
 Addr_Out2 = LCELL( _EQ007 $  Addr_In2);
  _EQ007 =  Addr_In_o &  Addr_In_z & !Addr_In2 &  _LC071
         #  Addr_In_o &  Addr_In_z &  Addr_In2 & !_LC071;

-- Node name is 'Addr_Out3' 
-- Equation name is 'Addr_Out3', location is LC080, type is output.
 Addr_Out3 = LCELL( _EQ008 $  GND);
  _EQ008 =  Addr_In_o &  Addr_In_z & !_LC033 &  _LC066
         # !Addr_In_o &  _LC027 & !_LC033
         # !Addr_In_z &  _LC027 & !_LC033
         #  Addr_In3 &  _LC033;

-- Node name is 'Addr_Out4' 
-- Equation name is 'Addr_Out4', location is LC073, type is output.
 Addr_Out4 = LCELL( _EQ009 $  Addr_In4);
  _EQ009 =  Addr_In_o &  Addr_In_z &  _LC067
         # !Addr_In_z &  _LC018
         # !Addr_In_o &  _LC018;

-- Node name is 'BYTE_LANE0' 
-- Equation name is 'BYTE_LANE0', location is LC099, type is output.
-- _LC099 borrows parallel expanders from _LC098 
 BYTE_LANE0 = LCELL( _EQ010 $  GND);
  _EQ010 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & !_LC071 & 
              _LC077 & !_LC081 & !_LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC071 &  _LC074 &  _LC078 & !_LC079 & !_LC081 & !_LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC071 & !_LC081 & 
             !_LC105 &  LTT1_2;

-- Node name is 'BYTE_LANE1' 
-- Equation name is 'BYTE_LANE1', location is LC101, type is output.
-- _LC101 borrows parallel expanders from _LC100 
 BYTE_LANE1 = LCELL( _EQ011 $  GND);
  _EQ011 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & !_LC071 & 
              _LC077 & !_LC081 &  _LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC071 &  _LC074 &  _LC078 & !_LC079 & !_LC081 &  _LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC071 & !_LC081 & 
              _LC105 &  LTT1_2;

-- Node name is 'BYTE_LANE2' 
-- Equation name is 'BYTE_LANE2', location is LC104, type is output.
-- _LC104 borrows parallel expanders from _LC103 
 BYTE_LANE2 = LCELL( _EQ012 $  GND);
  _EQ012 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & !_LC071 & 
              _LC077 &  _LC081 & !_LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC071 &  _LC074 &  _LC078 & !_LC079 &  _LC081 & !_LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC071 &  _LC081 & 
             !_LC105 &  LTT1_2;

-- Node name is 'BYTE_LANE3' 
-- Equation name is 'BYTE_LANE3', location is LC107, type is output.
-- _LC107 borrows parallel expanders from _LC106 
 BYTE_LANE3 = LCELL( _EQ013 $  GND);
  _EQ013 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & !_LC071 & 
              _LC077 &  _LC081 &  _LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC071 &  _LC074 &  _LC078 & !_LC079 &  _LC081 &  _LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC071 &  _LC081 & 
              _LC105 &  LTT1_2;

-- Node name is 'BYTE_LANE4' 
-- Equation name is 'BYTE_LANE4', location is LC083, type is output.
-- _LC083 borrows parallel expanders from _LC082 
 BYTE_LANE4 = LCELL( _EQ014 $  GND);
  _EQ014 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 &  _LC071 & 
              _LC077 & !_LC081 & !_LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         #  _LC071 &  _LC074 &  _LC078 & !_LC079 & !_LC081 & !_LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 &  _LC071 & !_LC081 & 
             !_LC105 &  LTT1_2;

-- Node name is 'BYTE_LANE5' 
-- Equation name is 'BYTE_LANE5', location is LC091, type is output.
-- _LC091 borrows parallel expanders from _LC090 
 BYTE_LANE5 = LCELL( _EQ015 $  GND);
  _EQ015 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 &  _LC071 & 
              _LC077 & !_LC081 &  _LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         #  _LC071 &  _LC074 &  _LC078 & !_LC079 & !_LC081 &  _LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 &  _LC071 & !_LC081 & 
              _LC105 &  LTT1_2;

-- Node name is 'BYTE_LANE6' 
-- Equation name is 'BYTE_LANE6', location is LC088, type is output.
-- _LC088 borrows parallel expanders from _LC087 
 BYTE_LANE6 = LCELL( _EQ016 $  GND);
  _EQ016 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 &  _LC071 & 
              _LC077 &  _LC081 & !_LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         #  _LC071 &  _LC074 &  _LC078 & !_LC079 &  _LC081 & !_LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 &  _LC071 &  _LC081 & 
             !_LC105 &  LTT1_2;

-- Node name is 'BYTE_LANE7' 
-- Equation name is 'BYTE_LANE7', location is LC093, type is output.
-- _LC093 borrows parallel expanders from _LC092 
 BYTE_LANE7 = LCELL( _EQ017 $  GND);
  _EQ017 = !Addr_In_o & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 & 
             !_LC074 &  _LC077 & !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !_LC019 & !_LC020 & !_LC023 &  _LC068 & !_LC069 &  _LC071 & 
              _LC077 &  _LC081 &  _LC105 &  LTT1_2
         # !Addr_In_o & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC074 & 
             !_LC078 & !_LC079 & !_LC110 &  LTT1_2
         #  _LC071 &  _LC074 &  _LC078 & !_LC079 &  _LC081 &  _LC105 & 
             !_LC110 &  LTT1_2
         # !_LC022 &  _LC026 & !_LC029 &  _LC030 &  _LC071 &  _LC081 & 
              _LC105 &  LTT1_2;

-- Node name is 'C/R_MUX' 
-- Equation name is 'C/R_MUX', location is LC072, type is output.
 C/R_MUX = LCELL( _EQ018 $  GND);
  _EQ018 = !_LC029 &  _LC030;

-- Node name is 'E_CLOCK' = '|io:162.E' from file "io.tdf" line 30, column 2
-- Equation name is 'E_CLOCK', type is output 
 E_CLOCK = TFFE( _EQ019, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ019 = !_LC019 & !_LC020 & !_LC023;

-- Node name is '~196~1' = 'LTSIZ0' 
-- Equation name is '~196~1', location is LC041, type is buried.
LTSIZ0   = DFFE( TSIZ2 $  GND,  _EQ020,  VCC,  VCC,  VCC);
  _EQ020 = !_LC034 &  _LC036 & !_LC039;

-- Node name is '~196~2' = 'LTSIZ1' 
-- Equation name is '~196~2', location is LC042, type is buried.
LTSIZ1   = DFFE( TSIZ1 $  GND,  _EQ021,  VCC,  VCC,  VCC);
  _EQ021 = !_LC034 &  _LC036 & !_LC039;

-- Node name is '~196~3' = 'LTSIZ2' 
-- Equation name is '~196~3', location is LC044, type is buried.
LTSIZ2   = DFFE( TSIZ0 $  GND,  _EQ022,  VCC,  VCC,  VCC);
  _EQ022 = !_LC034 &  _LC036 & !_LC039;

-- Node name is 'LTT1_2' = ':193' 
-- Equation name is 'LTT1_2', type is output 
 LTT1_2  = DFFE( TT1 $  GND,  _EQ023,  VCC,  VCC,  VCC);
  _EQ023 = !_LC034 &  _LC036 & !_LC039;

-- Node name is 'LTT1' = '~193~1' 
-- Equation name is 'LTT1', location is LC037, type is output.
 LTT1    = DFFE( TT1 $  GND,  _EQ023,  VCC,  VCC,  VCC);

-- Node name is 'XR' = '|io:162.XR' from file "io.tdf" line 31, column 2
-- Equation name is 'XR', type is output 
 XR      = TFFE( _EQ024,  E_CLOCK, GLOBAL( /RESET),  VCC,  VCC);
  _EQ024 = !_LC015 & !_LC028 & !_LC086;

-- Node name is '|abus:127|addr_state~1' from file "abus.tdf" line 15, column 2
-- Equation name is '_LC039', type is buried 
_LC039   = TFFE( _EQ025, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ025 = !_LC034 &  _LC039 &  _LC102 &  /TS
         #  _LC036 &  _LC039
         # !_LC034 &  _LC036;

-- Node name is '|abus:127|addr_state~2' from file "abus.tdf" line 15, column 2
-- Equation name is '_LC036', type is buried 
_LC036   = DFFE( _EQ026 $  GND, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ026 =  _LC034 & !_LC036 &  _LC039 &  _LC102
         # !_LC034 & !_LC036 &  _LC102 & !/TS
         # !_LC034 & !_LC036 & !_LC039 & !/TS
         # !_LC034 &  _LC036 &  _LC039;

-- Node name is '|abus:127|addr_state~3' from file "abus.tdf" line 15, column 2
-- Equation name is '_LC034', type is buried 
_LC034   = DFFE( _EQ027 $  GND, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ027 =  _LC034 & !_LC036 &  _LC039 & !_LC102
         # !_LC036 &  _LC039 & !_LC102 & !/TS;

-- Node name is '|dbus:129|data_state~1' from file "dbus.tdf" line 16, column 2
-- Equation name is '_LC097', type is buried 
_LC097   = TFFE( _EQ028, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ028 = !_LC097 &  _LC108 &  _LC109
         #  _LC097 &  _LC102 & !_LC109;

-- Node name is '|dbus:129|data_state~2' from file "dbus.tdf" line 16, column 2
-- Equation name is '_LC109', type is buried 
_LC109   = TFFE( _EQ029, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ029 = !_LC034 &  _LC036 & !_LC039 & !_LC097 & !_LC109
         #  _LC097 &  _LC109 &  _LC111
         #  _LC097 & !_LC102 & !_LC109;

-- Node name is '|io:162|E_clock~1' from file "io.tdf" line 23, column 2
-- Equation name is '_LC020', type is buried 
_LC020   = TFFE(!_EQ030, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ030 = !_LC019 & !_LC020 & !_LC023;

-- Node name is '|io:162|E_clock~2' from file "io.tdf" line 23, column 2
-- Equation name is '_LC019', type is buried 
_LC019   = TFFE( _EQ031, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ031 =  _LC019 &  _LC023
         # !_LC020;

-- Node name is '|io:162|E_clock~3' from file "io.tdf" line 23, column 2
-- Equation name is '_LC023', type is buried 
_LC023   = TFFE( _EQ032, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ032 =  _LC019 &  _LC020 &  _LC023
         # !_LC019 & !_LC020;

-- Node name is '|io:162|io_state~1~fit~in1' from file "io.tdf" line 18, column 2
-- Equation name is '_LC095', type is buried 
-- synthesized logic cell 
_LC095   = DFFE( _EQ033 $  _LC077, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ033 = !Addr_In_o &  Addr_In_z & !_LC068 & !_LC077 & !_LC095 & !_LC097 & 
              _LC109
         # !E_CLOCK & !_LC019 &  _LC020 &  _LC023 &  _LC077
         #  _LC068 &  _LC077
         #  _LC077 & !_LC095;

-- Node name is '|io:162|io_state~1' from file "io.tdf" line 18, column 2
-- Equation name is '_LC069', type is buried 
_LC069   = LCELL( _LC095 $  GND);

-- Node name is '|io:162|io_state~2' from file "io.tdf" line 18, column 2
-- Equation name is '_LC068', type is buried 
_LC068   = DFFE( _EQ034 $  GND, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ034 =  E_CLOCK & !_LC069 &  _LC077
         #  _LC068 & !_LC069 &  _LC077;

-- Node name is '|io:162|io_state~3' from file "io.tdf" line 18, column 2
-- Equation name is '_LC077', type is buried 
_LC077   = TFFE( _EQ035, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ035 = !Addr_In_o &  Addr_In_z & !_LC068 & !_LC077 & !_LC095 & !_LC097 & 
              _LC109
         #  _LC068 &  _LC069 &  _LC077
         # !E_CLOCK &  _LC068 &  _LC077;

-- Node name is '|io:162|XR_clock~1' from file "io.tdf" line 27, column 2
-- Equation name is '_LC086', type is buried 
_LC086   = TFFE(!_EQ036,  E_CLOCK, GLOBAL( /RESET),  VCC,  VCC);
  _EQ036 =  _LC015 &  _LC028 & !_LC086;

-- Node name is '|io:162|XR_clock~2' from file "io.tdf" line 27, column 2
-- Equation name is '_LC015', type is buried 
_LC015   = DFFE( _EQ037 $  GND,  E_CLOCK, GLOBAL( /RESET),  VCC,  VCC);
  _EQ037 =  _LC015 & !_LC028 &  _LC086
         # !_LC015 &  _LC028 & !_LC086;

-- Node name is '|io:162|XR_clock~3' from file "io.tdf" line 27, column 2
-- Equation name is '_LC028', type is buried 
_LC028   = DFFE( _EQ038 $  GND,  E_CLOCK, GLOBAL( /RESET),  VCC,  VCC);
  _EQ038 = !_LC015 &  _LC028 &  _LC086
         # !_LC015 & !_LC028 & !_LC086;

-- Node name is '|ram:132|B_COUNT0' = '|ram:132.ao3' from file "ram.tdf" line 36, column 9
-- Equation name is '_LC027', type is buried 
_LC027   = DFFE( _EQ039 $  GND, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ039 = !_LC022 &  _LC026 & !_LC027 & !_LC029 &  _LC030 & !_LC033
         # !_LC022 & !_LC026 &  _LC027 & !_LC029 &  _LC030
         #  _LC022 &  _LC027 & !_LC029 &  _LC030;

-- Node name is '|ram:132|B_COUNT1' from file "ram.tdf" line 36, column 9
-- Equation name is '_LC018', type is buried 
_LC018   = DFFE( _EQ040 $  GND, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ040 = !_LC018 & !_LC022 &  _LC026 &  _LC027 & !_LC029 &  _LC030 & 
             !_LC033
         #  _LC018 & !_LC022 &  _LC026 & !_LC027 & !_LC029 &  _LC030 & 
             !_LC033
         #  _LC018 & !_LC022 & !_LC026 & !_LC029 &  _LC030
         #  _LC018 &  _LC022 & !_LC029 &  _LC030;

-- Node name is '|ram:132|CAS_FF' from file "ram.tdf" line 34, column 10
-- Equation name is '_LC017', type is buried 
_LC017   = DFFE( _EQ041 $  GND, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ041 =  _LC022 &  _LC026 &  _LC029 & !_LC030
         # !_LC022 & !_LC026 &  _LC029 & !_LC030
         # !_LC026 & !_LC029 &  _LC030;

-- Node name is '|ram:132|REFRESH' = '|ram:132.ram_refresh' from file "ram.tdf" line 34, column 18
-- Equation name is '_LC113', type is buried 
_LC113   = DFFE( _EQ042 $  _LC026, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ042 = !_LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC029 & !_LC030 & !_LC116 & 
             !_LC123
         # !_LC026 &  _LC029 & !_LC030 &  _LC113
         # !_LC022 &  _LC026 & !_LC029 & !_LC113
         #  _LC026 &  _LC030;

-- Node name is '|ram:132|ram_state~1' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC022', type is buried 
-- _LC022 borrows parallel expanders from _LC021 
_LC022   = DFFE( _EQ043 $  GND, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ043 = !_LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC116 & !_LC123
         # !_LC018 & !_LC022 & !_LC029 &  _LC030 & !_LC033
         # !_LC022 & !_LC027 & !_LC029 &  _LC030 & !_LC033
         # !Addr_In_z & !_LC022 & !_LC026 & !_LC097 &  _LC109
         # !_LC022 &  _LC029 & !_LC030 & !Speed_Select_0
         # !_LC022 &  _LC026 & !_LC029 & !_LC030
         # !_LC022 & !_LC026 &  _LC029
         # !_LC022 & !_LC026 &  _LC030;

-- Node name is '|ram:132|ram_state~2' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC026', type is buried 
-- _LC026 borrows parallel expanders from _LC025 
_LC026   = TFFE( _EQ044, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ044 = !_LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC029 & !_LC030 & !_LC116 & !_LC123
         # !_LC022 &  _LC026 & !_LC029 & !_LC030
         #  _LC022 &  _LC026 &  _LC029
         # !_LC022 &  _LC029 &  _LC030
         #  _LC022 & !_LC029 &  _LC030
         #  _LC022 &  _LC029 & !_LC030;

-- Node name is '|ram:132|ram_state~3~fit~in1' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC127', type is buried 
-- _LC127 borrows parallel expanders from _LC126 
-- synthesized logic cell 
_LC127   = DFFE( _EQ045 $ !_LC029, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ045 = !_LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC029 & !_LC116 & !_LC123 & !_LC127
         #  _LC018 & !_LC022 &  _LC026 &  _LC027 & !_LC029
         # !_LC022 &  _LC026 & !_LC029 &  _LC033
         # !_LC026 &  _LC029 &  _LC127
         #  _LC026 & !_LC029 & !_LC127
         #  _LC022 & !_LC029 & !_LC127
         # !_LC029 &  _LC097 & !_LC127
         #  Addr_In_z & !_LC029 & !_LC127
         # !_LC029 & !_LC109 & !_LC127;

-- Node name is '|ram:132|ram_state~3' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC030', type is buried 
_LC030   = LCELL( _LC127 $  GND);

-- Node name is '|ram:132|ram_state~4' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC029', type is buried 
_LC029   = TFFE( _EQ046, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ046 = !_LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC029 & !_LC030 & !_LC116 & 
             !_LC123
         # !Addr_In_z & !_LC022 & !_LC026 & !_LC029 & !_LC030 & !_LC097 & 
              _LC109
         #  _LC026 &  _LC029 &  _LC030
         # !_LC022 &  _LC026 &  _LC029
         # !_LC022 &  _LC029 &  _LC030;

-- Node name is '|ram:132|R_COUNT0' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC016', type is buried 
_LC016   = TFFE(!_EQ047, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ047 =  _LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 &  _LC116 & !_LC123 &  Speed_Select_0
         #  _LC003 &  _LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC116 &  _LC123 & !Speed_Select_0;

-- Node name is '|ram:132|R_COUNT1' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC012', type is buried 
_LC012   = TFFE( _LC016, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);

-- Node name is '|ram:132|R_COUNT2' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC010', type is buried 
_LC010   = TFFE( _EQ048, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ048 =  _LC012 &  _LC016;

-- Node name is '|ram:132|R_COUNT3' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC014', type is buried 
_LC014   = TFFE( _EQ049, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ049 =  _LC010 &  _LC012 &  _LC016;

-- Node name is '|ram:132|R_COUNT4' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC005', type is buried 
_LC005   = TFFE( _EQ050, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ050 =  _LC003 &  _LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC029 & !_LC030 & !_LC116 & 
              _LC123 & !Speed_Select_0
         #  _LC010 &  _LC012 &  _LC014 &  _LC016;

-- Node name is '|ram:132|R_COUNT5' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC008', type is buried 
_LC008   = TFFE( _EQ051, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ051 =  _LC005 &  _LC010 &  _LC012 &  _LC014 &  _LC016;

-- Node name is '|ram:132|R_COUNT6' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC116', type is buried 
_LC116   = TFFE( _EQ052, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ052 =  _LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC029 & !_LC030 &  _LC116 & 
             !_LC123 &  Speed_Select_0
         #  _LC005 &  _LC008 &  _LC010 &  _LC012 &  _LC014 &  _LC016;

-- Node name is '|ram:132|R_COUNT7' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC123', type is buried 
_LC123   = TFFE( _EQ053, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ053 =  _LC003 &  _LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC029 & !_LC030 & !_LC116 & 
              _LC123 & !Speed_Select_0
         #  _LC005 &  _LC008 &  _LC010 &  _LC012 &  _LC014 &  _LC016 & 
              _LC116;

-- Node name is '|ram:132|R_COUNT8' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC003', type is buried 
_LC003   = TFFE( _EQ054, GLOBAL( PCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ054 =  _LC003 & !_LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC029 & !_LC030 &  _LC116 & 
             !_LC123 &  Speed_Select_0
         #  _LC003 &  _LC005 & !_LC008 & !_LC010 & !_LC012 & !_LC014 & 
             !_LC016 & !_LC022 & !_LC026 & !_LC029 & !_LC030 & !_LC116 & 
              _LC123 & !Speed_Select_0
         #  _LC005 &  _LC008 &  _LC010 &  _LC012 &  _LC014 &  _LC016 & 
              _LC116 &  _LC123;

-- Node name is '|rom:154|COUNTER0' = '|rom:154.ao0' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC105', type is buried 
_LC105   = DFFE( _EQ055 $  GND, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ055 = !_LC074 & !_LC078 &  _LC079 & !_LC105 & !_LC110
         #  _LC074 & !_LC078 &  _LC105 & !_LC110
         #  _LC079 &  _LC105 &  _LC110
         #  _LC078 &  _LC105;

-- Node name is '|rom:154|COUNTER1' = '|rom:154.ao1' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC081', type is buried 
_LC081   = TFFE( _EQ056, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ056 = !_LC074 & !_LC078 &  _LC079 & !_LC081 &  _LC105 & !_LC110
         # !_LC074 & !_LC078 &  _LC081 &  _LC105 & !_LC110
         # !_LC078 & !_LC079 &  _LC081 &  _LC110
         # !_LC074 & !_LC078 & !_LC079 &  _LC081;

-- Node name is '|rom:154|COUNTER2' = '|rom:154.ao2' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC071', type is buried 
_LC071   = TFFE( _EQ057, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ057 = !_LC071 & !_LC074 & !_LC078 &  _LC079 &  _LC081 &  _LC105 & 
             !_LC110
         #  _LC071 & !_LC074 & !_LC078 &  _LC081 &  _LC105 & !_LC110
         #  _LC071 & !_LC078 & !_LC079 &  _LC110
         #  _LC071 & !_LC074 & !_LC078 & !_LC079;

-- Node name is '|rom:154|COUNTER3' = '|rom:154.ao3' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC066', type is buried 
-- _LC066 borrows parallel expanders from _LC065 
_LC066   = TFFE( _EQ058, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ058 = !_LC066 &  _LC071 & !_LC074 & !_LC078 &  _LC079 &  _LC081 & 
              _LC105 & !_LC110
         #  _LC066 &  _LC071 & !_LC074 & !_LC078 &  _LC081 &  _LC105 & 
             !_LC110
         #  Addr_In0 & !_LC066 & !_LC074 & !_LC078 & !_LC079 &  _LC110
         #  _LC066 &  _LC074 & !_LC078 & !_LC079 &  _LC110
         # !Addr_In0 &  _LC066 & !_LC078 & !_LC079 &  _LC110
         #  _LC066 & !_LC074 & !_LC078 & !_LC079 & !_LC110;

-- Node name is '|rom:154|COUNTER4~fit~in1' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC002', type is buried 
-- _LC002 borrows parallel expanders from _LC001 
-- synthesized logic cell 
_LC002   = TFFE( _EQ059, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ059 = !_LC002 &  _LC066 &  _LC071 & !_LC074 & !_LC078 &  _LC079 & 
              _LC081 &  _LC105 & !_LC110
         #  _LC002 &  _LC066 &  _LC071 & !_LC074 & !_LC078 &  _LC081 & 
              _LC105 & !_LC110
         #  Addr_In1 & !_LC002 & !_LC074 & !_LC078 & !_LC079 &  _LC110
         #  _LC002 &  _LC074 & !_LC078 & !_LC079 &  _LC110
         # !Addr_In1 &  _LC002 & !_LC078 & !_LC079 &  _LC110
         #  _LC002 & !_LC074 & !_LC078 & !_LC079 & !_LC110;

-- Node name is '|rom:154|COUNTER4' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC067', type is buried 
_LC067   = LCELL( _LC002 $  GND);

-- Node name is '|rom:154|rom_state~1' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC078', type is buried 
_LC078   = TFFE(!_EQ060, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ060 =  _LC066 &  _LC067 &  _LC071 &  _LC074 &  _LC078 & !_LC079 & 
              _LC081 &  _LC105 & !_LC110
         #  _LC033 &  _LC071 &  _LC074 &  _LC078 & !_LC079 &  _LC081 & 
              _LC105 & !_LC110
         # !_LC074 & !_LC078 & !_LC079 & !_LC110
         # !_LC078 &  _LC079 &  _LC110;

-- Node name is '|rom:154|rom_state~2' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC074', type is buried 
_LC074   = DFFE( _EQ061 $  GND, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ061 =  Addr_In_o &  Addr_In_z & !_LC033 & !_LC078 & !_LC079 & !_LC097 & 
              _LC109 & !_LC110 &  LTT1_2
         #  _LC078 &  _LC079 & !_LC110
         #  _LC074 & !_LC078 & !_LC110;

-- Node name is '|rom:154|rom_state~3~fit~in1' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC007', type is buried 
-- _LC007 borrows parallel expanders from _LC006 
-- synthesized logic cell 
_LC007   = DFFE( _EQ062 $ !_LC110, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ062 =  _LC066 &  _LC067 &  _LC071 &  _LC074 &  _LC078 &  _LC081 & 
              _LC105 & !_LC110
         #  _LC033 &  _LC071 &  _LC074 &  _LC078 &  _LC081 &  _LC105 & 
             !_LC110
         #  _LC007 &  _LC074 &  _LC078 & !_LC110
         # !_LC007 & !_LC074 &  _LC078 & !_LC110
         # !_LC007 & !_LC078;

-- Node name is '|rom:154|rom_state~3' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC079', type is buried 
_LC079   = LCELL( _LC007 $  GND);

-- Node name is '|rom:154|rom_state~4' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC110', type is buried 
_LC110   = DFFE( _EQ063 $  GND, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ063 =  Addr_In_o &  Addr_In_z & !_LC074 & !_LC078 & !_LC079 & !_LC097 & 
              _LC109 & !_LC110 &  LTT1_2;

-- Node name is '/AACK' 
-- Equation name is '/AACK', location is LC043, type is output.
 /AACK   = LCELL( _EQ064 $  VCC);
  _EQ064 = !_LC034 &  _LC036 & !_LC039;

-- Node name is '/CAS0' 
-- Equation name is '/CAS0', location is LC038, type is output.
 /CAS0   = LCELL( _EQ065 $  VCC);
  _EQ065 = !Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017
         #  _LC017 &  _LC113
         #  _LC017 & !_LC033;

-- Node name is '/CAS1' 
-- Equation name is '/CAS1', location is LC049, type is output.
 /CAS1   = LCELL( _EQ066 $ !_LC017);
  _EQ066 = !Addr_In0 &  _LC017 &  _LC033 & !_LC113 &  LTSIZ0 & !LTSIZ1 & 
             !LTSIZ2
         #  Addr_In0 &  _LC017 &  _LC033 & !_LC113 & !LTSIZ0 & !LTSIZ1 & 
             !LTSIZ2
         #  Addr_In2 &  _LC017 &  _LC033 & !_LC113
         #  Addr_In1 &  _LC017 &  _LC033 & !_LC113;

-- Node name is '/CAS2' 
-- Equation name is '/CAS2', location is LC061, type is output.
-- _LC061 borrows parallel expanders from _LC060 
 /CAS2   = LCELL( _EQ067 $ !_LC017);
  _EQ067 = !Addr_In0 & !Addr_In1 &  _LC017 &  _LC033 & !_LC113 & !LTSIZ0 & 
              LTSIZ1 & !LTSIZ2
         #  Addr_In1 &  _LC017 &  _LC033 & !_LC113 &  LTSIZ0 &  LTSIZ1 & 
              LTSIZ2
         # !Addr_In1 &  _LC017 &  _LC033 & !_LC113 &  LTSIZ0 & !LTSIZ1 & 
             !LTSIZ2
         #  Addr_In1 &  _LC017 &  _LC033 & !_LC113 & !LTSIZ0 & !LTSIZ1 & 
             !LTSIZ2
         #  Addr_In0 &  _LC017 &  _LC033 & !_LC113 & !LTSIZ1 & !LTSIZ2
         #  Addr_In0 &  Addr_In1 &  _LC017 &  _LC033 & !_LC113
         #  Addr_In2 &  _LC017 &  _LC033 & !_LC113;

-- Node name is '/CAS3' 
-- Equation name is '/CAS3', location is LC053, type is output.
-- _LC053 borrows parallel expanders from _LC052 
 /CAS3   = LCELL( _EQ068 $  VCC);
  _EQ068 =  Addr_In0 & !Addr_In2 &  _LC017 &  LTSIZ0 &  LTSIZ1 & !LTSIZ2
         #  Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ0 & !LTSIZ1
         # !Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 & !LTSIZ0 & !LTSIZ1
         #  Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ1 & !LTSIZ2
         # !Addr_In0 & !Addr_In2 &  _LC017 & !LTSIZ0 &  LTSIZ2
         # !Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ2
         # !Addr_In2 &  _LC017 & !LTSIZ1 &  LTSIZ2
         #  _LC017 &  _LC113
         #  _LC017 & !_LC033;

-- Node name is '/CAS4' 
-- Equation name is '/CAS4', location is LC064, type is output.
-- _LC064 borrows parallel expanders from _LC063 and _LC062 
 /CAS4   = LCELL( _EQ069 $  VCC);
  _EQ069 = !Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 & !LTSIZ0 & !LTSIZ1 & 
              LTSIZ2
         # !Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 & !LTSIZ0 & !LTSIZ1 & 
             !LTSIZ2
         #  Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ0 &  LTSIZ1 & !LTSIZ2
         #  Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ1 & !LTSIZ2
         # !Addr_In0 & !Addr_In2 &  _LC017 & !LTSIZ0 &  LTSIZ1 &  LTSIZ2
         # !Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  LTSIZ1 & !LTSIZ2
         # !Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  LTSIZ0 & !LTSIZ2
         # !Addr_In2 &  _LC017 &  LTSIZ0 & !LTSIZ1 &  LTSIZ2
         #  Addr_In0 & !Addr_In2 &  _LC017 & !LTSIZ1 &  LTSIZ2
         #  Addr_In1 & !Addr_In2 &  _LC017 & !LTSIZ1 &  LTSIZ2
         # !Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ1 &  LTSIZ2
         #  _LC017 &  _LC113
         #  _LC017 & !_LC033;

-- Node name is '/CAS5' 
-- Equation name is '/CAS5', location is LC059, type is output.
-- _LC059 borrows parallel expanders from _LC058 and _LC057 
 /CAS5   = LCELL( _EQ070 $  VCC);
  _EQ070 =  Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ0 &  LTSIZ1 & 
             !LTSIZ2
         # !Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 & !LTSIZ0 & !LTSIZ1 & 
              LTSIZ2
         # !Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 & !LTSIZ0 & !LTSIZ1 & 
             !LTSIZ2
         #  Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ0 &  LTSIZ2
         #  Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  LTSIZ0 & !LTSIZ2
         # !Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 & !LTSIZ0 &  LTSIZ2
         # !Addr_In1 &  Addr_In2 &  _LC017 &  LTSIZ1 & !LTSIZ2
         #  Addr_In1 & !Addr_In2 &  _LC017 & !LTSIZ1 &  LTSIZ2
         # !Addr_In1 & !Addr_In2 &  _LC017 &  LTSIZ1 &  LTSIZ2
         #  _LC017 &  _LC113
         #  _LC017 & !_LC033;

-- Node name is '/CAS6' 
-- Equation name is '/CAS6', location is LC056, type is output.
-- _LC056 borrows parallel expanders from _LC055 and _LC054 
 /CAS6   = LCELL( _EQ071 $  VCC);
  _EQ071 = !Addr_In0 &  Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 & !LTSIZ1 & !LTSIZ2
         # !Addr_In0 &  Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 &  LTSIZ1 & !LTSIZ2
         # !Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 &  LTSIZ1 & !LTSIZ2
         # !Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 & !LTSIZ1 &  LTSIZ2
         # !Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 &  LTSIZ1 &  LTSIZ2
         # !Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 &  LTSIZ1 &  LTSIZ2
         # !Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 & !LTSIZ1 &  LTSIZ2
         # !Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 & !LTSIZ1 & !LTSIZ2
         #  Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ1 & !LTSIZ2
         #  Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ1 &  LTSIZ2
         #  Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ1 &  LTSIZ2
         #  _LC017 & !_LC033 & !_LC113
         #  _LC017 &  _LC113;

-- Node name is '/CAS7' 
-- Equation name is '/CAS7', location is LC051, type is output.
-- _LC051 borrows parallel expanders from _LC050 
 /CAS7   = LCELL( _EQ072 $  VCC);
  _EQ072 =  Addr_In0 &  Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 & !LTSIZ1 & !LTSIZ2
         #  Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 &  LTSIZ1 & !LTSIZ2
         #  Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 & !LTSIZ1 &  LTSIZ2
         #  Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
              LTSIZ0 &  LTSIZ1 &  LTSIZ2
         # !Addr_In0 &  Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 &  LTSIZ1 & !LTSIZ2
         # !Addr_In0 &  Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 &  LTSIZ1 &  LTSIZ2
         # !Addr_In0 & !Addr_In1 &  Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 & !LTSIZ1 &  LTSIZ2
         # !Addr_In0 & !Addr_In1 & !Addr_In2 &  _LC017 &  _LC033 & !_LC113 & 
             !LTSIZ0 & !LTSIZ1 & !LTSIZ2
         #  _LC017 & !_LC033 & !_LC113
         #  _LC017 &  _LC113;

-- Node name is '/CS_IO' 
-- Equation name is '/CS_IO', location is LC046, type is output.
 /CS_IO  = LCELL( _EQ073 $  VCC);
  _EQ073 = !Addr_In_o &  Addr_In_z;

-- Node name is '/CS_RAMIO1' 
-- Equation name is '/CS_RAMIO1', location is LC117, type is output.
 /CS_RAMIO1 = LCELL( _EQ074 $  GND);
  _EQ074 =  Addr_In_o &  Addr_In_z;

-- Node name is '/CS_RAMIO2' 
-- Equation name is '/CS_RAMIO2', location is LC118, type is output.
 /CS_RAMIO2 = LCELL( _EQ075 $  GND);
  _EQ075 =  Addr_In_o &  Addr_In_z;

-- Node name is '/CS_ROM' 
-- Equation name is '/CS_ROM', location is LC040, type is output.
 /CS_ROM = LCELL( _EQ076 $  VCC);
  _EQ076 =  Addr_In_o &  Addr_In_z &  LTT1_2;

-- Node name is '/CS_ROM2' 
-- Equation name is '/CS_ROM2', location is LC125, type is output.
 /CS_ROM2 = LCELL( _EQ077 $  VCC);
  _EQ077 =  Addr_In_o &  Addr_In_z &  LTT1_2;

-- Node name is '/RAS' = '|ram:132|RAS_FF' from file "ram.tdf" line 34, column 2
-- Equation name is '/RAS', type is output 
/RAS     = _LC075~NOT;
_LC075~NOT = DFFE( _EQ078 $ !_LC029, GLOBAL( 2xPCLK),  VCC,  /RESET,  VCC);
  _EQ078 =  _LC026 &  _LC030
         #  _LC022 &  _LC026
         # !_LC029 &  _LC030;

-- Node name is '/TA' 
-- Equation name is '/TA', location is LC065, type is output.
-- _LC065 lends parallel expanders to _LC066 
 /TA     = LCELL( _EQ079 $  VCC);
  _EQ079 =  _LC097 & !_LC109;

-- Node name is '/we_ram' 
-- Equation name is '/we_ram', location is LC085, type is output.
 /we_ram = LCELL( _EQ080 $  VCC);
  _EQ080 = !_LC029 &  _LC030 & !LTT1_2;

-- Node name is ':126' 
-- Equation name is '_LC108', type is buried 
_LC108   = TFFE( _EQ081, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ081 = !Addr_In_z &  _LC022 & !_LC026 &  _LC029 &  _LC030 & !_LC108
         #  Addr_In_o &  Addr_In_z & !_LC078 & !_LC079 & !_LC108 &  _LC110
         # !Addr_In_o &  Addr_In_z & !_LC068 &  _LC069 &  _LC077 & !_LC108
         #  _LC097 &  _LC108 &  _LC109;

-- Node name is ':181' 
-- Equation name is '_LC111', type is buried 
_LC111   = TFFE( _EQ082, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ082 =  Addr_In_o &  Addr_In_z &  _LC071 &  _LC074 &  _LC078 & !_LC079 & 
              _LC081 &  _LC105 & !_LC110 & !_LC111
         # !Addr_In_o &  Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & 
             !_LC069 &  _LC077 & !_LC111
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 &  _LC030 & !_LC111
         #  _LC097 & !_LC109 &  _LC111;

-- Node name is ':182' 
-- Equation name is '_LC102', type is buried 
_LC102   = TFFE( _EQ083, GLOBAL( 2xPCLK), GLOBAL( /RESET),  VCC,  VCC);
  _EQ083 = !Addr_In_o &  Addr_In_z & !_LC019 & !_LC020 & !_LC023 &  _LC068 & 
             !_LC069 &  _LC077 & !_LC102
         #  Addr_In_o &  Addr_In_z & !_LC074 &  _LC078 & !_LC079 & !_LC102 & 
             !_LC110
         # !Addr_In_z & !_LC022 &  _LC026 & !_LC029 & !_LC030 & !_LC102 & 
             !_LC113
         # !_LC097 &  _LC102 & !_LC109;

-- Node name is ':184' 
-- Equation name is '_LC033', type is buried 
_LC033   = DFFE( /TBST $  GND,  _EQ084,  VCC,  VCC,  VCC);
  _EQ084 = !_LC034 &  _LC036 & !_LC039;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                         c:\bean\toplev.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = FAST

      Logic option settings in 'FAST' style for 'MAX7000E' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = off
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = off
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = off
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic I/O Cell Registers        = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 10

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:28
   Database Builder                       00:00:27
   Logic Synthesizer                      00:00:32
   Partitioner                            00:00:06
   Fitter                                 00:00:17
   Timing SNF Extractor                   00:00:11
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:02:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,169K
