Project Information                                             c:\bean\mb.rpt

MAX+plus II Compiler Report File
Version 7.0 08/26/96
Compiled: 04/24/97 18:12:33

Copyright (c) Altera Corporation, 1996. This file may contain proprietary and confidential
information of Altera Corporation that may be used, copied, and disclosed only pursuant to
the terms of Altera's Program License Agreement. Altera makes no claim to any end-user or
third-party proprietary information that also may be contained in this file. This notice
must be contained as part of this text at all times.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

mb        EPM7128ELC84-10  10       43       0      118     78          92 %

User Pins:                 10       43       0  



Project Information                                             c:\bean\mb.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Symbol "OUTPUT" (ID |toplev:2|:203) overlaps another symbol
Warning: Symbol "NOT" (ID |toplev:2|:165) overlaps another symbol
Warning: Symbol "NOT" (ID |toplev:2|:145) overlaps another symbol
Warning: Symbol "AND2" (ID |toplev:2|:168) overlaps another symbol
Warning: Symbol "AND2" (ID |toplev:2|:167) overlaps another symbol
Warning: Symbol "AND2" (ID |toplev:2|:178) overlaps another symbol
Warning: Line 12, File c:\bean\ram.tdf:
   Symbolic name "ai3" was declared but never used
Warning: Line 12, File c:\bean\rom.tdf:
   Symbolic name "M66" was declared but never used
Warning: Line 12, File c:\bean\rom.tdf:
   Symbolic name "M60" was declared but never used
Warning: Line 11, File c:\bean\rom.tdf:
   Symbolic name "ai2" was declared but never used
Warning: Line 11, File c:\bean\rom.tdf:
   Symbolic name "ai3" was declared but never used
Warning: Line 5, File c:\bean\8and.tdf:
   Group MSB will be "byte_lane_in0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 6, File c:\bean\8and.tdf:
   Group MSB will be "byte_lane_out0", overrides default order of bits or BIT0=LSB in Options Statement
Warning: Line 5, File c:\bean\addr3mux.tdf:
   Symbolic name "inaddr0" was declared but never used
Warning: Line 5, File c:\bean\addr3mux.tdf:
   Symbolic name "inaddr1" was declared but never used
Warning: Line 5, File c:\bean\addr3mux.tdf:
   Symbolic name "inaddr2" was declared but never used
Warning: Line 5, File c:\bean\addr3mux.tdf:
   Symbolic name "inaddr4" was declared but never used
Warning: Ignored unnecessary INPUT pin 'adr2'
Warning: Ignored unnecessary INPUT pin 'adr3'
Warning: Ignored unnecessary INPUT pin 'adr4'
Warning: Ignored unnecessary INPUT pin 'adr5'
Warning: Ignored unnecessary INPUT pin 'adr6'
Warning: Ignored unnecessary INPUT pin 'adr7'
Warning: Ignored unnecessary INPUT pin 'adr8'
Warning: Ignored unnecessary INPUT pin 'adr9'
Warning: Ignored unnecessary INPUT pin 'adr10'
Warning: Ignored unnecessary INPUT pin 'adr11'
Warning: Ignored unnecessary INPUT pin 'adr12'
Warning: Ignored unnecessary INPUT pin 'adr13'
Warning: Ignored unnecessary INPUT pin 'adr14'
Warning: Ignored unnecessary INPUT pin 'adr15'
Warning: Ignored unnecessary INPUT pin 'adr16'
Warning: Ignored unnecessary INPUT pin 'adr17'
Warning: Ignored unnecessary INPUT pin 'adr18'
Warning: Ignored unnecessary INPUT pin 'adr19'
Warning: Ignored unnecessary INPUT pin 'adr20'
Warning: Ignored unnecessary INPUT pin 'adr21'
Warning: Ignored unnecessary INPUT pin 'adr22'
Warning: Ignored unnecessary INPUT pin 'adr23'
Warning: Ignored unnecessary INPUT pin 'adr24'
Warning: Ignored unnecessary INPUT pin 'adr25'
Warning: Ignored unnecessary INPUT pin 'adr26'


Project Information                                             c:\bean\mb.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'pclk' chosen for auto global Clock
INFO: Signal '2xpclk' chosen for auto global Clock


Project Information                                             c:\bean\mb.rpt

** STATE MACHINE ASSIGNMENTS **


|601sim:1|601state:1.a_out: MACHINE
        OF BITS (
           |601sim:1|601state:1|ABB,
           !|601sim:1|601state:1|TS,
           |601sim:1|601state:1.split
        )
        WITH STATES (
                               D = B"000", 
                               T = B"110", 
                              AD = B"100", 
                              TD = B"111", 
                             ADD = B"101", 
                              DD = B"001", 
                              TX = B"010", 
                             TXX = B"011"
);


|601sim:1|601state:1.t_out: MACHINE
        OF BITS (
           |601sim:1|601state:1|ta0,
           |601sim:1|601state:1|ta1,
           |601sim:1|601state:1|ta2
        )
        WITH STATES (
                          Treset = B"101", 
                            NoTA = B"000", 
                          Got1TA = B"010", 
                          Got2TA = B"110", 
                          Got3TA = B"100", 
                           Burst = B"001", 
                           Done1 = B"011", 
                           Done2 = B"111"
);


|601sim:1|601state:1.d_out: MACHINE
        OF BITS (
           |601sim:1|601state:1|olap,
           !|601sim:1|601state:1|DBB
        )
        WITH STATES (
                            IDLE = B"00", 
                            DBB1 = B"01", 
                            DBB2 = B"11", 
                           Pause = B"10"
);


|601sim:1|601cycle:13|cycle_type: MACHINE
        OF BITS (
           |601sim:1.A0,
           |601sim:1.A1,
           |601sim:1.TT1,
           |601sim:1.TSIZ1
        )
        WITH STATES (
                            Idle = B"0010", 
                           RdROM = B"1110", 
                        RdBstROM = B"1111", 
                          WrACIA = B"1000", 
                          RdACIA = B"1010", 
                        WrBstRAM = B"0001", 
                        RdBstRAM = B"0011", 
                           WrRAM = B"0000", 
                         Unused4 = B"0100", 
                         Unused5 = B"0101", 
                         Unused6 = B"0110", 
                         Unused7 = B"0111", 
                         Unused9 = B"1001", 
                         UnusedB = B"1011", 
                         UnusedC = B"1100", 
                         UnusedD = B"1101"
);


|toplev:2|abus:127.addr_st: MACHINE
        OF BITS (
           |toplev:2|abus:127|addr_state~3,
           |toplev:2|abus:127|addr_state~2,
           |toplev:2|abus:127|addr_state~1
        )
        WITH STATES (
                       ADDR_IDLE = B"000", 
                      ADDR_LATCH = B"010", 
                    ADDR_LATCHED = B"001", 
                     ADDR_BACKUP = B"101", 
                     ADDR_OPENUP = B"011", 
                         ADDR_X1 = B"111", 
                         ADDR_X2 = B"110", 
                         ADDR_X3 = B"100"
);


|toplev:2|dbus:129.data_st: MACHINE
        OF BITS (
           |toplev:2|dbus:129|data_state~2,
           |toplev:2|dbus:129|data_state~1
        )
        WITH STATES (
                       DATA_IDLE = B"00", 
                         DATA_GO = B"10", 
                       DATA_WAIT = B"11", 
                         DATA_TA = B"01"
);


|toplev:2|ram:132|ram_state: MACHINE
        OF BITS (
           |toplev:2|ram:132|ram_state~4,
           |toplev:2|ram:132|ram_state~3,
           |toplev:2|ram:132|ram_state~2,
           |toplev:2|ram:132|ram_state~1
        )
        WITH STATES (
                        RAM_IDLE = B"0000", 
                         RAM_CAS = B"1100", 
                         RAM_RAS = B"0111", 
                       RAM_WAIT1 = B"0101", 
                       RAM_WAIT2 = B"0100", 
                       RAM_WAIT3 = B"0110", 
                       RAM_WAIT4 = B"0011", 
                        RAM_RET1 = B"0010", 
                        RAM_RET2 = B"0001", 
                     RAM_COUNTER = B"1110", 
                      RAM_COUNT1 = B"1011", 
                      RAM_COUNT2 = B"1001", 
                      RAM_COUNT3 = B"1000", 
                      RAM_COUNT4 = B"1010", 
                     RAM_RASHOLD = B"1101", 
                          RAM_X1 = B"1111"
);


|toplev:2|rom:154|rom_state: MACHINE
        OF BITS (
           |toplev:2|rom:154|rom_state~4,
           |toplev:2|rom:154|rom_state~3,
           |toplev:2|rom:154|rom_state~2,
           |toplev:2|rom:154|rom_state~1
        )
        WITH STATES (
                        ROM_IDLE = B"0000", 
                       ROM_COUNT = B"1001", 
                      ROM_TCOUNT = B"1011", 
                        ROM_WAIT = B"0100", 
                       ROM_WAIT2 = B"0111", 
                       ROM_WAIT3 = B"0010", 
                       ROM_WAIT4 = B"0110", 
                       ROM_LATCH = B"0011", 
                        ROM_INCR = B"0101", 
                      ROM_LASTTA = B"0001", 
                          ROM_X1 = B"1101", 
                          ROM_X2 = B"1111", 
                          ROM_X3 = B"1000", 
                          ROM_X4 = B"1010", 
                          ROM_X5 = B"1100", 
                          ROM_X6 = B"1110"
);


|toplev:2|io:162|io_state: MACHINE
        OF BITS (
           |toplev:2|io:162|io_state~4,
           |toplev:2|io:162|io_state~3,
           |toplev:2|io:162|io_state~2,
           |toplev:2|io:162|io_state~1
        )
        WITH STATES (
                         IO_IDLE = B"0000", 
                           IO_EH = B"1100", 
                           IO_EL = B"1000", 
                       IO_CSHOLD = B"1010", 
                           IO_CS = B"1011", 
                           IO_RW = B"1101", 
                        IO_READ1 = B"0101", 
                        IO_READ2 = B"0100", 
                        IO_READ3 = B"0110", 
                        IO_READ4 = B"0111", 
                        IO_READ5 = B"0010", 
                        IO_READ6 = B"0011", 
                        IO_READ7 = B"0001", 
                        IO_WRITE = B"1001", 
                           IO_X1 = B"1111", 
                           IO_X2 = B"1110"
);


|toplev:2|io:162|E_clock: MACHINE
        OF BITS (
           |toplev:2|io:162|E_clock~4,
           |toplev:2|io:162|E_clock~3,
           |toplev:2|io:162|E_clock~2,
           |toplev:2|io:162|E_clock~1
        )
        WITH STATES (
                             E_0 = B"0000", 
                             E_1 = B"1000", 
                             E_2 = B"0111", 
                             E_3 = B"0110", 
                             E_4 = B"0101", 
                             E_5 = B"0100", 
                             E_6 = B"0011", 
                             E_7 = B"0010", 
                             E_8 = B"0001", 
                             E_9 = B"1001", 
                             E_A = B"1010", 
                             E_B = B"1011", 
                             E_C = B"1100", 
                             E_D = B"1101", 
                             E_E = B"1110", 
                             E_F = B"1111"
);



Project Information                                             c:\bean\mb.rpt

** FILE HIERARCHY **



|601sim:1|
|601sim:1|601state:1|
|601sim:1|601cycle:13|
|toplev:2|
|toplev:2|abus:127|
|toplev:2|dbus:129|
|toplev:2|ram:132|
|toplev:2|rom:154|
|toplev:2|io:162|
|toplev:2|busmux:175|
|toplev:2|busmux:175|lpm_mux:43|
|toplev:2|busmux:175|lpm_mux:43|altshift:external_latency_ffs|
|toplev:2|busmux:175|lpm_mux:43|muxlut:60|
|toplev:2|busmux:175|lpm_mux:43|muxlut:73|
|toplev:2|busmux:175|lpm_mux:43|muxlut:86|
|toplev:2|busmux:175|lpm_mux:43|muxlut:99|
|toplev:2|busmux:175|lpm_mux:43|muxlut:112|
|toplev:2|3mux:177|
|toplev:2|8and:200|
|toplev:2|addr3mux:207|
|adrlatch:7|
|adrlatch:7|74374:1|
|adrlatch:7|74374:3|
|adrlatch:7|74374:2|
|adrlatch:7|74374:4|


Device-Specific Information:                                    c:\bean\mb.rpt
mb

***** Logic for device 'mb' compiled without errors.




Device: EPM7128ELC84-10
Turbo: ON
Security: OFF


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** ERROR SUMMARY **

Info: Chip 'mb' in device 'EPM7128ELC84-10' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                   a                                                           
                   d                                                           
                   d                 R                                         
                   r                 E                                         
                   _                 S     2     /                             
                /  l  /  /     /     E     x     r                    t     /  
                a  a  c  c     c     R     p     e  p     a  a  /     s     t  
                a  t  a  a  G  a  /  V  V  c  G  s  c  G  d  d  d  V  i  t  b  
                c  c  s  s  N  s  g  E  C  l  N  e  l  N  r  r  b  C  z  t  s  
                k  h  0  4  D  5  0  D  C  k  D  t  k  D  1  0  b  C  2  1  t  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
     /cas1 | 12                                                              74 | tsiz1 
       VCC | 13                                                              73 | tsiz0 
      /ras | 14                                                              72 | GND 
     adr27 | 15                                                              71 | RESERVED 
     adr30 | 16                                                              70 | RESERVED 
     adr29 | 17                                                              69 | RESERVED 
   e_clock | 18                                                              68 | /cas3 
       GND | 19                                                              67 | RESERVED 
  RESERVED | 20                                                              66 | VCC 
  spdsel_0 | 21                                                              65 | RESERVED 
  spdsel_1 | 22                       EPM7128ELC84-10                        64 | /cas2 
byte_lane4 | 23                                                              63 | RESERVED 
byte_lane6 | 24                                                              62 | addr_out2 
byte_lane3 | 25                                                              61 | addr_out4 
       VCC | 26                                                              60 | /cs_io 
byte_lane0 | 27                                                              59 | GND 
byte_lane7 | 28                                                              58 | RESERVED 
byte_lane1 | 29                                                              57 | /ta 
byte_lane5 | 30                                                              56 | RESERVED 
byte_lane2 | 31                                                              55 | addr_out3 
       GND | 32                                                              54 | /cs_rom 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                a  a  R  a  a  V  /  c  a  G  V  L  /  R  G  R  R  /  /  /  V  
                d  d  E  d  c  C  w  /  d  N  C  T  c  E  N  E  E  c  c  t  C  
                d  d  S  r  i  C  e  r  r  D  C  T  a  S  D  S  S  a  s  s  C  
                r  r  E  2  a     _  _  3        1  s  E     E  E  s  _        
                _  _  R  8  /     r  m  1           6  R     R  R  7  r        
                o  o  V     c     a  u                 V     V  V     a        
                u  u  E     s     m  x                 E     E  E     m        
                t  t  D                                D     D  D              
                0  1                                                           
                                                                               


N.C. = Not Connected.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                                    c:\bean\mb.rpt
mb

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    13/16( 81%)   7/ 8( 87%)  16/16(100%)  33/36( 91%) 
B:    LC17 - LC32    14/16( 87%)   7/ 8( 87%)  16/16(100%)  33/36( 91%) 
C:    LC33 - LC48    14/16( 87%)   8/ 8(100%)  16/16(100%)  33/36( 91%) 
D:    LC49 - LC64    14/16( 87%)   7/ 8( 87%)  13/16( 81%)  34/36( 94%) 
E:    LC65 - LC80    16/16(100%)   5/ 8( 62%)  15/16( 93%)  34/36( 94%) 
F:    LC81 - LC96    15/16( 93%)   6/ 8( 75%)  16/16(100%)  34/36( 94%) 
G:   LC97 - LC112    16/16(100%)   2/ 8( 25%)  16/16(100%)  34/36( 94%) 
H:  LC113 - LC128    16/16(100%)   8/ 8(100%)  12/16( 75%)  21/36( 58%) 


Total dedicated input pins used:                 3/4    ( 75%)
Total I/O pins used:                            50/64   ( 78%)
Total logic cells used:                        118/128  ( 92%)
Total shareable expanders used:                 78/128  ( 60%)
Total Turbo logic cells used:                  118/128  ( 92%)
Total shareable expanders not available (n/a):  42/128  ( 32%)

Total input pins required:                      10
Total input registers required:                  0
Total output pins required:                     43
Total bidirectional pins required:               0
Total logic cells required:                    118
Total flipflops required:                       71
Total shareable expanders in database:          73

Synthesized logic cells:                        17/ 128 ( 13%)



Device-Specific Information:                                    c:\bean\mb.rpt
mb

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  15   (29)  (B)      INPUT              0      0   0    0    0    0    1  adr27
  36   (57)  (D)      INPUT              0      0   0    0    0    0    1  adr28
  17   (25)  (B)      INPUT              0      0   0    0    0    0    1  adr29
  16   (27)  (B)      INPUT              0      0   0    0    0    0    1  adr30
  41   (49)  (D)      INPUT              0      0   0    0    0    0    1  adr31
  83      -   -       INPUT              0      0   0    0    0    0    0  pclk
  84      -   -       INPUT              0      0   0    0    0   11   48  /reset
  21   (19)  (B)      INPUT              0      0   0    0    0    0   17  spdsel_0
  22   (17)  (B)      INPUT              0      0   0    0    0    0   20  spdsel_1
   2      -   -       INPUT              0      0   0    0    0    0    0  2xpclk


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  11      5    A     OUTPUT     t        0      0   0    0    3    0    0  /aack
  37     56    D     OUTPUT     t        0      0   0    0    4    0    0  acia/cs
  10      6    A     OUTPUT     t        0      0   0    0    3    0    0  addr_latch
  33     64    D     OUTPUT     t        0      0   0    0    4    0    0  addr_out0
  34     61    D     OUTPUT     t        0      0   0    0    4    0    0  addr_out1
  62     96    F     OUTPUT     t        0      0   0    0    4    0    0  addr_out2
  55     85    F     OUTPUT     t        0      0   0    0    6    0    0  addr_out3
  61     94    F     OUTPUT     t        0      0   0    0    5    0    0  addr_out4
  80    126    H         FF  +  t        1      0   1    1    6    8    0  adr0 (|601sim:1|601cycle:13|a0~)
  81    128    H         FF  +  t        1      0   1    1    6    7    1  adr1 (|601sim:1|601cycle:13|a1~)
  27     43    C     OUTPUT     t        1      1   0    0   12    0    0  byte_lane0
  29     38    C     OUTPUT     t        1      1   0    0   12    0    0  byte_lane1
  31     35    C     OUTPUT     t        1      1   0    0   12    0    0  byte_lane2
  25     45    C     OUTPUT     t        1      1   0    0   12    0    0  byte_lane3
  23     48    C     OUTPUT     t        1      1   0    0   12    0    0  byte_lane4
  30     37    C     OUTPUT     t        1      1   0    0   12    0    0  byte_lane5
  24     46    C     OUTPUT     t        5      1   0    0   18    0    0  byte_lane6
  28     40    C     OUTPUT     t        5      1   0    0   18    0    0  byte_lane7
   9      8    A     OUTPUT     t        0      0   0    0    6    0    0  /cas0
  12      3    A     OUTPUT     t        1      0   1    0    9    0    0  /cas1
  64     99    G     OUTPUT     t        6      3   1    0    9    0    0  /cas2
  68    105    G     OUTPUT     t        6      3   1    0    9    0    0  /cas3
   8     11    A     OUTPUT     t        5      4   1    0   10    0    0  /cas4
   6     13    A     OUTPUT     t        8      4   1    0    9    0    0  /cas5
  45     67    E     OUTPUT     t        6      1   1    0   10    0    0  /cas6
  50     75    E     OUTPUT     t        3      1   1    0   10    0    0  /cas7
  40     51    D     OUTPUT     t        0      0   0    0    2    0    0  c/r_mux
  60     93    F     OUTPUT     t        0      0   0    0    2    0    0  /cs_io
  51     77    E         FF     t        0      0   0    0    4   15   12  /cs_ram
  54     83    F     OUTPUT     t        0      0   0    0    2    0    0  /cs_rom
  79    125    H         FF  +  t !      0      0   0    1    7    2    1  /dbb
  18     24    B         FF  +  t        0      0   0    1    4    0    3  e_clock (|toplev:2|io:162|E_FF)
   5     14    A     OUTPUT     t        0      0   0    0    1    0    0  /g0 (|toplev:2|:202)
  44     65    E         FF     t        0      0   0    0    4    9   12  LTT1 (|toplev:2|:193)
  14     32    B         FF  +  t !      1      0   1    1    4    0    0  /ras
  57     88    F     OUTPUT     t        0      0   0    0    2    0    0  /ta
  75    118    H         FF  +  t !      1      0   1    1    7    1    3  /tbst
  52     80    E         FF  +  t !      0      0   0    1    3    3    6  /ts
  73    115    H         FF  +  t        2      1   1    1    6    0    1  tsiz0 (|601sim:1|601cycle:13|:44)
  74    117    H         FF  +  t        2      1   0    1    6    6    1  tsiz1 (|601sim:1|601cycle:13|tsiz1~)
  77    123    H         FF  +  t        0      0   0    1    6    0    1  tsiz2 (|601sim:1|601cycle:13|:43)
  76    120    H         FF  +  t        3      1   1    1    6    8    0  tt1 (|601sim:1|601cycle:13|tt1~)
  39     53    D     OUTPUT     t        0      0   0    0    3    0    0  /we_ram


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     15    A       DFFE     t        0      0   0    1    3    1    0  |adrlatch:7|74374:1|:16
 (46)    69    E       DFFE     t        0      0   0    1    3    1    0  |adrlatch:7|74374:1|:17
   -     71    E       DFFE     t        0      0   0    1    3    9    2  |adrlatch:7|74374:1|:18
   -     70    E       DFFE     t        0      0   0    1    3    9    3  |adrlatch:7|74374:1|:19
   -     68    E       DFFE     t        0      0   0    1    3    9    3  |adrlatch:7|74374:1|:20
   -    113    H       DFFE     t        0      0   0    0    4    7    9  |adrlatch:7|74374:3|:14
 (48)    72    E       TFFE  +  t        0      0   0    1    5    4   15  |toplev:2|abus:127|addr_state~1
   -     76    E       DFFE  +  t        1      0   1    1    5    4   15  |toplev:2|abus:127|addr_state~2
   -     78    E       DFFE  +  t        0      0   0    1    5    4   15  |toplev:2|abus:127|addr_state~3
   -     89    F       TFFE  +  t        0      0   0    1    4    2   16  |toplev:2|dbus:129|data_state~1
   -    121    H       TFFE  +  t        0      0   0    1    7    2   16  |toplev:2|dbus:129|data_state~2
 (20)    21    B       DFFE  +  t        0      0   0    1    4    1    4  |toplev:2|io:162|E_clock~1
 (21)    19    B       DFFE  +  t        0      0   0    1    4    1    4  |toplev:2|io:162|E_clock~2
   -     30    B       TFFE  +  t        0      0   0    1    4    1    4  |toplev:2|io:162|E_clock~3
 (15)    29    B       DFFE  +  t        0      0   0    1    4    1    4  |toplev:2|io:162|E_clock~4
   -     60    D       DFFE  +  t        0      0   0    3    4    9   15  |toplev:2|io:162|io_state~1
 (35)    59    D       DFFE  +  t        3      0   1    1    5    9   15  |toplev:2|io:162|io_state~2
   -     62    D       SOFT   s t        1      0   1    2    9    0    1  |toplev:2|io:162|io_state~3~1
   -     39    C       DFFE  +  t        3      0   0    2    7    9   15  |toplev:2|io:162|io_state~3
   -    108    G       TFFE  +  t        1      0   1    1    9    9   15  |toplev:2|io:162|io_state~4
   -     87    F       DFFE  +  t        0      0   0    1    6    1    4  |toplev:2|ram:132.ao3 (|toplev:2|ram:132|B_COUNT0)
   -     95    F       DFFE  +  t        1      0   1    1    7    1    3  |toplev:2|ram:132|B_COUNT1
   -     42    C       DFFE  +  t        0      0   0    1    4    8    2  |toplev:2|ram:132|CAS_FF
   -     66    E       DFFE  +  t        6      1   1    3    7    3   31  |toplev:2|ram:132|ram_state~1
   -     50    D       DFFE  +  t        5      0   0    1   16    3   31  |toplev:2|ram:132|ram_state~2
   -     82    F       TFFE  +  t        5      2   0    3   16    5   31  |toplev:2|ram:132|ram_state~3
   -     81    F       TFFE  +  t        6      3   0    1   19    5   31  |toplev:2|ram:132|ram_state~4
 (41)    49    D       TFFE  +  t        2      1   1    3   13    0   17  |toplev:2|ram:132|R_COUNT0
   -     92    F       DFFE  +  t        1      1   0    3   13    0   18  |toplev:2|ram:132|R_COUNT1
   -     18    B       DFFE  +  t        3      0   1    3   13    0   18  |toplev:2|ram:132|R_COUNT2
   -     52    D       DFFE  +  t        2      0   0    3   13    0   18  |toplev:2|ram:132|R_COUNT3
   -     22    B       DFFE  +  t        2      0   0    3   14    0   18  |toplev:2|ram:132|R_COUNT4
   -     12    A       TFFE  +  t        2      0   1    3   13    0   18  |toplev:2|ram:132|R_COUNT5
  (4)    16    A       DFFE  +  t        2      0   1    3   14    0   17  |toplev:2|ram:132|R_COUNT6
   -     90    F       DFFE  +  t        2      0   1    3   14    0   17  |toplev:2|ram:132|R_COUNT7
   -     26    B       DFFE  +  t        2      0   1    3   15    0   18  |toplev:2|ram:132|R_COUNT8
 (58)    91    F       DFFE  +  t        3      0   1    1   14    8    3  |toplev:2.Refresh (|toplev:2|ram:132|REFRESH)
   -      1    A       SOFT   s t        1      0   1    0    7    1    0  |toplev~2./CAS4~1 (|toplev:2|ram:132|:137)
   -    102    G       SOFT   s t        0      0   0    0    9    2    0  |toplev~2./CAS6~1 (|toplev:2|ram:132|:139)
 (22)    17    B       SOFT   s t        1      0   1    2   13    0    1  |toplev:2|ram:132|~287~1
 (16)    27    B       SOFT   s t        1      0   1    2   13    0    1  |toplev:2|ram:132|~293~1
   -     20    B       SOFT   s t        0      0   0    2   13    0    1  |toplev:2|ram:132|~296~1
 (17)    25    B       SOFT   s t        1      0   1    2   13    0    1  |toplev:2|ram:132|~299~1
   -      7    A       SOFT   s t        1      0   1    0    6    0    1  |toplev:2|ram:132|~299~2
   -     63    D       TFFE  +  t        0      0   0    1    5    3   13  |toplev:2|rom:154.ao0 (|toplev:2|rom:154|COUNTER0)
   -     54    D       TFFE  +  t        0      0   0    1    6    3   12  |toplev:2|rom:154.ao1 (|toplev:2|rom:154|COUNTER1)
 (69)   107    G       TFFE  +  t        0      0   0    1    7    3   11  |toplev:2|rom:154.ao2 (|toplev:2|rom:154|COUNTER2)
   -     47    C       TFFE  +  t        2      0   1    1    9    1    3  |toplev:2|rom:154.ao3 (|toplev:2|rom:154|COUNTER3)
   -     34    C       TFFE  +  t        2      0   1    1   10    1    2  |toplev:2|rom:154|COUNTER4
   -    103    G       DFFE  +  t        1      0   1    2    9    8   19  |toplev:2|rom:154|rom_state~1
   -     98    G       TFFE  +  t        1      0   1    1   10    8   18  |toplev:2|rom:154|rom_state~2
   -     28    B       DFFE  +  t        5      0   1    2   10    8   19  |toplev:2|rom:154|rom_state~3
 (36)    57    D       DFFE  +  t        0      0   0    1    9    8   19  |toplev:2|rom:154|rom_state~4
 (65)   101    G       SOFT   s t        1      0   1    0   20    0    1  |toplev:2|3mux~177.done~1 (|toplev:2|3mux:177|:57)
 (71)   112    G       SOFT   s t        1      0   1    0   18    0    1  |toplev:2|3mux~177.lastta~1 (|toplev:2|3mux:177|:61)
   -     36    C       SOFT   s t        0      0   0    0   16    1    0  |toplev~2.BYTE_LANE5~1 (|toplev:2|8and:200|:46)
   -    106    G       SOFT   s t        0      0   0    0   16    1    0  |toplev~2.BYTE_LANE4~1 (|toplev:2|8and:200|:47)
   -    110    G       SOFT   s t        0      0   0    0   16    1    0  |toplev~2.BYTE_LANE3~1 (|toplev:2|8and:200|:48)
 (70)   109    G       SOFT   s t        0      0   0    0   16    1    0  |toplev~2.BYTE_LANE2~1 (|toplev:2|8and:200|:49)
   -    100    G       SOFT   s t        0      0   0    0   16    1    0  |toplev~2.BYTE_LANE1~1 (|toplev:2|8and:200|:50)
 (67)   104    G       SOFT   s t        1      0   1    0   15    8    0  |toplev~2.BYTE_LANE0~1 (|toplev:2|8and:200|:51)
   -    111    G       SOFT   s t        0      0   0    0   16    1    0  |toplev~2.BYTE_LANE0~2 (|toplev:2|8and:200|:51)
 (63)    97    G       TFFE  +  t        1      0   1    1   16    0    2  |toplev:2|:126
 (56)    86    F       TFFE  +  t        0      0   0    1    1    0    2  |toplev:2|:181
   -     33    C       TFFE  +  t        0      0   0    1    1    0    6  |toplev:2|:182
   -     10    A       DFFE     t        0      0   0    0    4    9    7  |toplev:2|:184
 (49)    73    E       DFFE     t        0      0   0    0    4    7    2  |toplev:2|LTSIZ0 (|toplev:2|~196~1)
   -    122    H       DFFE     t        0      0   0    0    4    7    2  |toplev:2|LTSIZ1 (|toplev:2|~196~2)
   -     74    E       DFFE     t        0      0   0    0    4    7    2  |toplev:2|LTSIZ2 (|toplev:2|~196~3)
   -     79    E       DFFE  +  t        0      0   0    1    6    8    2  |601sim:1|601state:1|ABB
   -    114    H       DFFE  +  t        0      0   0    1    3    1    1  |601sim:1|601state:1|olap
   -    119    H       DFFE  +  t        1      0   1    1    6    8    3  |601sim:1|601state:1.split (|601sim:1|601state:1|split~)
   -    116    H       TFFE  +  t        0      0   0    1    6    0    4  |601sim:1|601state:1|ta0
   -    124    H       TFFE  +  t        0      0   0    1    5    1    4  |601sim:1|601state:1|ta1
   -    127    H       TFFE  +  t        3      0   1    1    7    1    4  |601sim:1|601state:1|ta2


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                   Logic cells placed in LAB 'A'
        +------------------------- LC5 /aack
        | +----------------------- LC6 addr_latch
        | | +--------------------- LC15 |adrlatch:7|74374:1|:16
        | | | +------------------- LC8 /cas0
        | | | | +----------------- LC3 /cas1
        | | | | | +--------------- LC11 /cas4
        | | | | | | +------------- LC13 /cas5
        | | | | | | | +----------- LC14 /g0
        | | | | | | | | +--------- LC12 |toplev:2|ram:132|R_COUNT5
        | | | | | | | | | +------- LC16 |toplev:2|ram:132|R_COUNT6
        | | | | | | | | | | +----- LC1 |toplev~2./CAS4~1
        | | | | | | | | | | | +--- LC7 |toplev:2|ram:132|~299~2
        | | | | | | | | | | | | +- LC10 |toplev:2|:184
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'A':
LC12 -> - - - - - - - - * * - * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT5
LC16 -> - - - - - - - - * * - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT6
LC1  -> - - - - - * - - - - - - - | * - - - - - - - | <-- |toplev~2./CAS4~1
LC10 -> - - - * * * * - - - - - - | * * - - * * * - | <-- |toplev:2|:184

Pin
15   -> - - * - - - - - - - - - - | * - - - - - - - | <-- adr27
83   -> - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> - - - - - - - - * * - - - | * * * * * * * * | <-- /reset
21   -> - - - - - - - - * * - - - | * * - * * * - - | <-- spdsel_0
22   -> - - - - - - - - * * - - - | * * * * * * * - | <-- spdsel_1
2    -> - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC71 -> - - - * * * * - - - * - - | * - - - * * * - | <-- |adrlatch:7|74374:1|:18
LC70 -> - - - * * * * - - - * - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:19
LC68 -> - - - * * * * - - - * - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:20
LC125-> - - - - - - - * - - - - - | * - - - - - - * | <-- /dbb
LC118-> - - - - - - - - - - - - * | * - - - - - - * | <-- /tbst
LC72 -> * * * - - - - - - - - - * | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~1
LC76 -> * * * - - - - - - - - - * | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~2
LC78 -> * * * - - - - - - - - - * | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~3
LC42 -> - - - * * * * - - - * - - | * - - - * - * - | <-- |toplev:2|ram:132|CAS_FF
LC66 -> - - - - - - - - * * - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~1
LC50 -> - - - - - - - - * * - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~2
LC82 -> - - - - - - - - * * - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~3
LC81 -> - - - - - - - - * * - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~4
LC49 -> - - - - - - - - * * - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT0
LC92 -> - - - - - - - - * * - * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT1
LC18 -> - - - - - - - - * * - * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT2
LC52 -> - - - - - - - - * * - * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT3
LC22 -> - - - - - - - - * * - * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT4
LC90 -> - - - - - - - - * * - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT7
LC26 -> - - - - - - - - * * - * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT8
LC91 -> - - - * * * * - - - - - - | * - - - * * * - | <-- |toplev:2.Refresh
LC27 -> - - - - - - - - - * - - - | * - - - - - - - | <-- |toplev:2|ram:132|~293~1
LC73 -> - - - - * * * - - - * - - | * - - - * - * - | <-- |toplev:2|LTSIZ0
LC122-> - - - - * * * - - - * - - | * - - - * - * - | <-- |toplev:2|LTSIZ1
LC74 -> - - - - * * * - - - * - - | * - - - * - * - | <-- |toplev:2|LTSIZ2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                     Logic cells placed in LAB 'B'
        +--------------------------- LC24 e_clock
        | +------------------------- LC32 /ras
        | | +----------------------- LC21 |toplev:2|io:162|E_clock~1
        | | | +--------------------- LC19 |toplev:2|io:162|E_clock~2
        | | | | +------------------- LC30 |toplev:2|io:162|E_clock~3
        | | | | | +----------------- LC29 |toplev:2|io:162|E_clock~4
        | | | | | | +--------------- LC18 |toplev:2|ram:132|R_COUNT2
        | | | | | | | +------------- LC22 |toplev:2|ram:132|R_COUNT4
        | | | | | | | | +----------- LC26 |toplev:2|ram:132|R_COUNT8
        | | | | | | | | | +--------- LC17 |toplev:2|ram:132|~287~1
        | | | | | | | | | | +------- LC27 |toplev:2|ram:132|~293~1
        | | | | | | | | | | | +----- LC20 |toplev:2|ram:132|~296~1
        | | | | | | | | | | | | +--- LC25 |toplev:2|ram:132|~299~1
        | | | | | | | | | | | | | +- LC28 |toplev:2|rom:154|rom_state~3
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'B':
LC21 -> * - * * * * - - - - - - - - | - * - - - - - - | <-- |toplev:2|io:162|E_clock~1
LC19 -> * - * * * * - - - - - - - - | - * - - - - - - | <-- |toplev:2|io:162|E_clock~2
LC30 -> * - * * * * - - - - - - - - | - * - - - - - - | <-- |toplev:2|io:162|E_clock~3
LC29 -> * - * * * * - - - - - - - - | - * - - - - - - | <-- |toplev:2|io:162|E_clock~4
LC18 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT2
LC22 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT4
LC26 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT8
LC17 -> - - - - - - - * - - - - - - | - * - - - - - - | <-- |toplev:2|ram:132|~287~1
LC25 -> - - - - - - - - * - - - - - | - * - - - - - - | <-- |toplev:2|ram:132|~299~1
LC28 -> - - - - - - - - - - - - - * | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~3

Pin
83   -> - - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> * * * * * * * * * - - - - * | * * * * * * * * | <-- /reset
21   -> - - - - - - * * * * * * * - | * * - * * * - - | <-- spdsel_0
22   -> - - - - - - * * * * * * * * | * * * * * * * - | <-- spdsel_1
2    -> - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC66 -> - * - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~1
LC50 -> - * - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~2
LC82 -> - * - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~3
LC81 -> - * - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~4
LC49 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT0
LC92 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT1
LC52 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT3
LC12 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT5
LC16 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT6
LC90 -> - - - - - - * * * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT7
LC7  -> - - - - - - - - * - - - - - | - * - - - - - - | <-- |toplev:2|ram:132|~299~2
LC63 -> - - - - - - - - - - - - - * | - * * * - - * - | <-- |toplev:2|rom:154.ao0
LC54 -> - - - - - - - - - - - - - * | - * * * - - * - | <-- |toplev:2|rom:154.ao1
LC107-> - - - - - - - - - - - - - * | - * * - - * * - | <-- |toplev:2|rom:154.ao2
LC47 -> - - - - - - - - - - - - - * | - * * - - * - - | <-- |toplev:2|rom:154.ao3
LC34 -> - - - - - - - - - - - - - * | - * * - - * - - | <-- |toplev:2|rom:154|COUNTER4
LC103-> - - - - - - - - - - - - - * | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~1
LC98 -> - - - - - - - - - - - - - * | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~2
LC57 -> - - - - - - - - - - - - - * | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~4
LC10 -> - - - - - - - - - - - - - * | * * - - * * * - | <-- |toplev:2|:184


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                     Logic cells placed in LAB 'C'
        +--------------------------- LC43 byte_lane0
        | +------------------------- LC38 byte_lane1
        | | +----------------------- LC35 byte_lane2
        | | | +--------------------- LC45 byte_lane3
        | | | | +------------------- LC48 byte_lane4
        | | | | | +----------------- LC37 byte_lane5
        | | | | | | +--------------- LC46 byte_lane6
        | | | | | | | +------------- LC40 byte_lane7
        | | | | | | | | +----------- LC39 |toplev:2|io:162|io_state~3
        | | | | | | | | | +--------- LC42 |toplev:2|ram:132|CAS_FF
        | | | | | | | | | | +------- LC47 |toplev:2|rom:154.ao3
        | | | | | | | | | | | +----- LC34 |toplev:2|rom:154|COUNTER4
        | | | | | | | | | | | | +--- LC36 |toplev~2.BYTE_LANE5~1
        | | | | | | | | | | | | | +- LC33 |toplev:2|:182
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'C':
LC39 -> * * * * * * * * * - - - * - | - - * * - - * - | <-- |toplev:2|io:162|io_state~3
LC47 -> - - - - - - - - - - * * - - | - * * - - * - - | <-- |toplev:2|rom:154.ao3
LC34 -> - - - - - - - - - - - * - - | - * * - - * - - | <-- |toplev:2|rom:154|COUNTER4
LC36 -> - - - - - * - - - - - - - - | - - * - - - - - | <-- |toplev~2.BYTE_LANE5~1

Pin
83   -> - - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> - - - - - - - - * * * * - * | * * * * * * * * | <-- /reset
22   -> - - - - - - - - * - - - - - | * * * * * * * - | <-- spdsel_1
2    -> - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC70 -> - - - - - - - - - - - * - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:19
LC68 -> - - - - - - - - - - * - - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:20
LC77 -> * * * * * * * * - - - - - - | - - * * - * * - | <-- /cs_ram
LC24 -> - - - - - - - - * - - - - - | - - * * - - - - | <-- e_clock
LC65 -> * * * * * * * * * - - - * - | - - * * - - * - | <-- LTT1
LC60 -> * * * * * * * * * - - - * - | - - * * - - * - | <-- |toplev:2|io:162|io_state~1
LC59 -> * * * * * * * * * - - - * - | - - * * - - * - | <-- |toplev:2|io:162|io_state~2
LC62 -> - - - - - - - - * - - - - - | - - * - - - - - | <-- |toplev:2|io:162|io_state~3~1
LC108-> * * * * * * * * * - - - * - | - - * * - - * - | <-- |toplev:2|io:162|io_state~4
LC66 -> - - - - - - * * - * - - * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~1
LC50 -> - - - - - - * * - * - - * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~2
LC82 -> - - - - - - * * - * - - * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~3
LC81 -> - - - - - - * * - * - - * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~4
LC63 -> - - - - - - * * - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154.ao0
LC54 -> - - - - - - * * - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154.ao1
LC107-> - - - - - - * * - - * * * - | - * * - - * * - | <-- |toplev:2|rom:154.ao2
LC103-> * * * * * * * * - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~1
LC98 -> * * * * * * * * - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~2
LC28 -> * * * * * * * * - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~3
LC57 -> * * * * * * * * - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~4
LC112-> - - - - - - - - - - - - - * | - - * - - - - - | <-- |toplev:2|3mux~177.lastta~1
LC106-> - - - - * - - - - - - - - - | - - * - - - - - | <-- |toplev~2.BYTE_LANE4~1
LC110-> - - - * - - - - - - - - - - | - - * - - - - - | <-- |toplev~2.BYTE_LANE3~1
LC109-> - - * - - - - - - - - - - - | - - * - - - - - | <-- |toplev~2.BYTE_LANE2~1
LC100-> - * - - - - - - - - - - - - | - - * - - - - - | <-- |toplev~2.BYTE_LANE1~1
LC104-> * * * * * * * * - - - - - - | - - * - - - - - | <-- |toplev~2.BYTE_LANE0~1
LC111-> * - - - - - - - - - - - - - | - - * - - - - - | <-- |toplev~2.BYTE_LANE0~2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                     Logic cells placed in LAB 'D'
        +--------------------------- LC56 acia/cs
        | +------------------------- LC64 addr_out0
        | | +----------------------- LC61 addr_out1
        | | | +--------------------- LC51 c/r_mux
        | | | | +------------------- LC60 |toplev:2|io:162|io_state~1
        | | | | | +----------------- LC59 |toplev:2|io:162|io_state~2
        | | | | | | +--------------- LC62 |toplev:2|io:162|io_state~3~1
        | | | | | | | +------------- LC50 |toplev:2|ram:132|ram_state~2
        | | | | | | | | +----------- LC49 |toplev:2|ram:132|R_COUNT0
        | | | | | | | | | +--------- LC52 |toplev:2|ram:132|R_COUNT3
        | | | | | | | | | | +------- LC63 |toplev:2|rom:154.ao0
        | | | | | | | | | | | +----- LC54 |toplev:2|rom:154.ao1
        | | | | | | | | | | | | +--- LC57 |toplev:2|rom:154|rom_state~4
        | | | | | | | | | | | | | +- LC53 /we_ram
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'D':
LC60 -> * - - - * * * - - - - - - - | - - * * - - * - | <-- |toplev:2|io:162|io_state~1
LC59 -> * - - - * * * - - - - - - - | - - * * - - * - | <-- |toplev:2|io:162|io_state~2
LC50 -> - - - - - - - * * * - - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~2
LC49 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT0
LC52 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT3
LC63 -> - * - - - - - - - - * * - - | - * * * - - * - | <-- |toplev:2|rom:154.ao0
LC54 -> - - * - - - - - - - - * - - | - * * * - - * - | <-- |toplev:2|rom:154.ao1
LC57 -> - - - - - - - - - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~4

Pin
83   -> - - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> - - - - * * - * * * * * * - | * * * * * * * * | <-- /reset
21   -> - - - - * - * - * * - - - - | * * - * * * - - | <-- spdsel_0
22   -> - - - - * - * - * * - - - - | * * * * * * * - | <-- spdsel_1
2    -> - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC70 -> - - * - - - - - - - - - - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:19
LC68 -> - * - - - - - - - - - - - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:20
LC113-> - * * - - - * - - - - - * - | - - - * - * * - | <-- |adrlatch:7|74374:3|:14
LC77 -> - * * - - - * * - - - - * - | - - * * - * * - | <-- /cs_ram
LC24 -> - - - - - * * - - - - - - - | - - * * - - - - | <-- e_clock
LC65 -> - - - - - - - - - - - - * * | - - * * - - * - | <-- LTT1
LC89 -> - - - - - - * * - - - - * - | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~1
LC121-> - - - - - - * * - - - - * - | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~2
LC39 -> * - - - * * * - - - - - - - | - - * * - - * - | <-- |toplev:2|io:162|io_state~3
LC108-> * - - - * * * - - - - - - - | - - * * - - * - | <-- |toplev:2|io:162|io_state~4
LC66 -> - - - - - - - * * * - - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~1
LC82 -> - - - * - - - * * * - - - * | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~3
LC81 -> - - - * - - - * * * - - - * | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~4
LC92 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT1
LC18 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT2
LC22 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT4
LC12 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT5
LC16 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT6
LC90 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT7
LC26 -> - - - - - - - * * * - - - - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT8
LC103-> - - - - - - - - - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~1
LC98 -> - - - - - - - - - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~2
LC28 -> - - - - - - - - - - * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC69 |adrlatch:7|74374:1|:17
        | +----------------------------- LC71 |adrlatch:7|74374:1|:18
        | | +--------------------------- LC70 |adrlatch:7|74374:1|:19
        | | | +------------------------- LC68 |adrlatch:7|74374:1|:20
        | | | | +----------------------- LC67 /cas6
        | | | | | +--------------------- LC75 /cas7
        | | | | | | +------------------- LC77 /cs_ram
        | | | | | | | +----------------- LC65 LTT1
        | | | | | | | | +--------------- LC72 |toplev:2|abus:127|addr_state~1
        | | | | | | | | | +------------- LC76 |toplev:2|abus:127|addr_state~2
        | | | | | | | | | | +----------- LC78 |toplev:2|abus:127|addr_state~3
        | | | | | | | | | | | +--------- LC66 |toplev:2|ram:132|ram_state~1
        | | | | | | | | | | | | +------- LC73 |toplev:2|LTSIZ0
        | | | | | | | | | | | | | +----- LC74 |toplev:2|LTSIZ2
        | | | | | | | | | | | | | | +--- LC80 /ts
        | | | | | | | | | | | | | | | +- LC79 |601sim:1|601state:1|ABB
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC71 -> - - - - * * - - - - - - - - - - | * - - - * * * - | <-- |adrlatch:7|74374:1|:18
LC70 -> - - - - * * - - - - - - - - - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:19
LC68 -> - - - - * * - - - - - - - - - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:20
LC72 -> * * * * - - * * * * * - * * - * | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~1
LC76 -> * * * * - - * * * * * - * * - * | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~2
LC78 -> * * * * - - * * * * * - * * - * | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~3
LC66 -> - - - - - - - - - - - * - - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~1
LC73 -> - - - - * * - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|LTSIZ0
LC74 -> - - - - * * - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|LTSIZ2
LC80 -> - - - - - - - - * * * - - - * * | - - - - * - - * | <-- /ts
LC79 -> - - - - - - - - - - - - - - * * | - - - - * - - * | <-- |601sim:1|601state:1|ABB

Pin
36   -> * - - - - - - - - - - - - - - - | - - - - * - - - | <-- adr28
17   -> - * - - - - - - - - - - - - - - | - - - - * - - - | <-- adr29
16   -> - - * - - - - - - - - - - - - - | - - - - * - - - | <-- adr30
41   -> - - - * - - - - - - - - - - - - | - - - - * - - - | <-- adr31
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> - - - - - - - - * * * * - - * * | * * * * * * * * | <-- /reset
21   -> - - - - - - - - - - - * - - - - | * * - * * * - - | <-- spdsel_0
22   -> - - - - - - - - - - - * - - - - | * * * * * * * - | <-- spdsel_1
2    -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC126-> - - - - - - * - - - - - - - - - | - - - - * - - * | <-- adr0
LC87 -> - - - - - - - - - - - * - - - - | - - - - * * - - | <-- |toplev:2|ram:132.ao3
LC95 -> - - - - - - - - - - - * - - - - | - - - - * * - - | <-- |toplev:2|ram:132|B_COUNT1
LC42 -> - - - - * * - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|ram:132|CAS_FF
LC50 -> - - - - - - - - - - - * - - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~2
LC82 -> - - - - - - - - - - - * - - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~3
LC81 -> - - - - - - - - - - - * - - - - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~4
LC91 -> - - - - * * - - - - - - - - - - | * - - - * * * - | <-- |toplev:2.Refresh
LC102-> - - - - * * - - - - - - - - - - | - - - - * - - - | <-- |toplev~2./CAS6~1
LC33 -> - - - - - - - - * * * - - - - - | - - - - * * * * | <-- |toplev:2|:182
LC10 -> - - - - * * - - - - - * - - - - | * * - - * * * - | <-- |toplev:2|:184
LC122-> - - - - * * - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|LTSIZ1
LC115-> - - - - - - - - - - - - * - - - | - - - - * - - - | <-- tsiz0
LC123-> - - - - - - - - - - - - - * - - | - - - - * - - - | <-- tsiz2
LC120-> - - - - - - - * - - - - - - - - | - - - - * - - * | <-- tt1
LC119-> - - - - - - - - - - - - - - * * | - - - - * - - * | <-- |601sim:1|601state:1.split


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                       Logic cells placed in LAB 'F'
        +----------------------------- LC96 addr_out2
        | +--------------------------- LC85 addr_out3
        | | +------------------------- LC94 addr_out4
        | | | +----------------------- LC93 /cs_io
        | | | | +--------------------- LC83 /cs_rom
        | | | | | +------------------- LC88 /ta
        | | | | | | +----------------- LC89 |toplev:2|dbus:129|data_state~1
        | | | | | | | +--------------- LC87 |toplev:2|ram:132.ao3
        | | | | | | | | +------------- LC95 |toplev:2|ram:132|B_COUNT1
        | | | | | | | | | +----------- LC82 |toplev:2|ram:132|ram_state~3
        | | | | | | | | | | +--------- LC81 |toplev:2|ram:132|ram_state~4
        | | | | | | | | | | | +------- LC92 |toplev:2|ram:132|R_COUNT1
        | | | | | | | | | | | | +----- LC90 |toplev:2|ram:132|R_COUNT7
        | | | | | | | | | | | | | +--- LC91 |toplev:2.Refresh
        | | | | | | | | | | | | | | +- LC86 |toplev:2|:181
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC89 -> - - - - - * * - - * * - - - - | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~1
LC87 -> - * - - - - - * * - * - - - - | - - - - * * - - | <-- |toplev:2|ram:132.ao3
LC95 -> - - * - - - - - * - * - - - - | - - - - * * - - | <-- |toplev:2|ram:132|B_COUNT1
LC82 -> - - - - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~3
LC81 -> - - - - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~4
LC92 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT1
LC90 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT7
LC91 -> - - - - - - - - - - - - - * - | * - - - * * * - | <-- |toplev:2.Refresh

Pin
83   -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> - - - - - - * * * * * * * * * | * * * * * * * * | <-- /reset
21   -> - - - - - - - - - * - * * - - | * * - * * * - - | <-- spdsel_0
22   -> - - - - - - - - - * - * * - - | * * * * * * * - | <-- spdsel_1
2    -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC15 -> - - * - - - - - - - - - - - - | - - - - - * - - | <-- |adrlatch:7|74374:1|:16
LC69 -> - * - - - - - - - - - - - - - | - - - - - * - - | <-- |adrlatch:7|74374:1|:17
LC71 -> * - - - - - - - - - - - - - - | * - - - * * * - | <-- |adrlatch:7|74374:1|:18
LC113-> * * * * * - - - - - - - - - - | - - - * - * * - | <-- |adrlatch:7|74374:3|:14
LC77 -> * * * * * - - - - * * - - - - | - - * * - * * - | <-- /cs_ram
LC121-> - - - - - * * - - * * - - - - | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~2
LC66 -> - - - - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~1
LC50 -> - - - - - - - * * * * * * * - | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~2
LC49 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT0
LC18 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT2
LC52 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT3
LC22 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT4
LC12 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT5
LC16 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT6
LC26 -> - - - - - - - - - * * * * * - | * * - * - * - - | <-- |toplev:2|ram:132|R_COUNT8
LC20 -> - - - - - - - - - - - - * - - | - - - - - * - - | <-- |toplev:2|ram:132|~296~1
LC107-> * - - - - - - - - - - - - - - | - * * - - * * - | <-- |toplev:2|rom:154.ao2
LC47 -> - * - - - - - - - - - - - - - | - * * - - * - - | <-- |toplev:2|rom:154.ao3
LC34 -> - - * - - - - - - - - - - - - | - * * - - * - - | <-- |toplev:2|rom:154|COUNTER4
LC101-> - - - - - - - - - - - - - - * | - - - - - * - - | <-- |toplev:2|3mux~177.done~1
LC97 -> - - - - - - * - - - - - - - - | - - - - - * * - | <-- |toplev:2|:126
LC33 -> - - - - - - * - - - - - - - - | - - - - * * * * | <-- |toplev:2|:182
LC10 -> - * - - - - - * * - * - - - - | * * - - * * * - | <-- |toplev:2|:184


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                         Logic cells placed in LAB 'G'
        +------------------------------- LC99 /cas2
        | +----------------------------- LC105 /cas3
        | | +--------------------------- LC108 |toplev:2|io:162|io_state~4
        | | | +------------------------- LC102 |toplev~2./CAS6~1
        | | | | +----------------------- LC107 |toplev:2|rom:154.ao2
        | | | | | +--------------------- LC103 |toplev:2|rom:154|rom_state~1
        | | | | | | +------------------- LC98 |toplev:2|rom:154|rom_state~2
        | | | | | | | +----------------- LC101 |toplev:2|3mux~177.done~1
        | | | | | | | | +--------------- LC112 |toplev:2|3mux~177.lastta~1
        | | | | | | | | | +------------- LC106 |toplev~2.BYTE_LANE4~1
        | | | | | | | | | | +----------- LC110 |toplev~2.BYTE_LANE3~1
        | | | | | | | | | | | +--------- LC109 |toplev~2.BYTE_LANE2~1
        | | | | | | | | | | | | +------- LC100 |toplev~2.BYTE_LANE1~1
        | | | | | | | | | | | | | +----- LC104 |toplev~2.BYTE_LANE0~1
        | | | | | | | | | | | | | | +--- LC111 |toplev~2.BYTE_LANE0~2
        | | | | | | | | | | | | | | | +- LC97 |toplev:2|:126
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC108-> - - * - - - - * * * * * * * * * | - - * * - - * - | <-- |toplev:2|io:162|io_state~4
LC107-> - - - - * - - * - * * * * - * - | - * * - - * * - | <-- |toplev:2|rom:154.ao2
LC103-> - - - - * * * * * * * * * * * * | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~1
LC98 -> - - - - * * * * * * * * * * * - | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~2
LC97 -> - - - - - - - - - - - - - - - * | - - - - - * * - | <-- |toplev:2|:126

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> - - * - * * * - - - - - - - - * | * * * * * * * * | <-- /reset
22   -> - - - - - * - - - - - - - - - - | * * * * * * * - | <-- spdsel_1
2    -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC71 -> * * - * - - - - - - - - - - - - | * - - - * * * - | <-- |adrlatch:7|74374:1|:18
LC70 -> * * - * - - - - - - - - - - - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:19
LC68 -> * * - * - - - - - - - - - - - - | * - * * * - * - | <-- |adrlatch:7|74374:1|:20
LC113-> - - * - - * * * * - - - - * - * | - - - * - * * - | <-- |adrlatch:7|74374:3|:14
LC77 -> - - * - - * * * * - - - - * - * | - - * * - * * - | <-- /cs_ram
LC65 -> - - * - - * * - - * * * * * * - | - - * * - - * - | <-- LTT1
LC89 -> - - * - - * * * * - - - - - - * | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~1
LC121-> - - * - - * * * * - - - - - - * | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~2
LC60 -> - - * - - - - * * * * * * * * * | - - * * - - * - | <-- |toplev:2|io:162|io_state~1
LC59 -> - - * - - - - * * * * * * * * * | - - * * - - * - | <-- |toplev:2|io:162|io_state~2
LC39 -> - - * - - - - * * * * * * * * * | - - * * - - * - | <-- |toplev:2|io:162|io_state~3
LC42 -> * * - * - - - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|ram:132|CAS_FF
LC66 -> - - - - - - - * * * * * * * * * | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~1
LC50 -> - - - - - - - * * * * * * * * * | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~2
LC82 -> - - - - - - - * * * * * * * * * | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~3
LC81 -> - - - - - - - * * * * * * * * * | * * * * * * * - | <-- |toplev:2|ram:132|ram_state~4
LC91 -> * * - * - - - - * - - - - - - - | * - - - * * * - | <-- |toplev:2.Refresh
LC63 -> - - - - * - - * - * * * * - * - | - * * * - - * - | <-- |toplev:2|rom:154.ao0
LC54 -> - - - - * - - * - * * * * - * - | - * * * - - * - | <-- |toplev:2|rom:154.ao1
LC28 -> - - - - * * * * * * * * * * * * | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~3
LC57 -> - - - - * * * * * * * * * * * * | - * * * - - * - | <-- |toplev:2|rom:154|rom_state~4
LC86 -> - - - - - - - * - - - - - - - - | - - - - - - * * | <-- |toplev:2|:181
LC33 -> - - - - - - - - * - - - - - - - | - - - - * * * * | <-- |toplev:2|:182
LC10 -> * * - * - - * - - - - - - - - - | * * - - * * * - | <-- |toplev:2|:184
LC73 -> * * - * - - - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|LTSIZ0
LC122-> * * - * - - - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|LTSIZ1
LC74 -> * * - * - - - - - - - - - - - - | * - - - * - * - | <-- |toplev:2|LTSIZ2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC113 |adrlatch:7|74374:3|:14
        | +----------------------------- LC126 adr0
        | | +--------------------------- LC128 adr1
        | | | +------------------------- LC125 /dbb
        | | | | +----------------------- LC118 /tbst
        | | | | | +--------------------- LC121 |toplev:2|dbus:129|data_state~2
        | | | | | | +------------------- LC122 |toplev:2|LTSIZ1
        | | | | | | | +----------------- LC115 tsiz0
        | | | | | | | | +--------------- LC117 tsiz1
        | | | | | | | | | +------------- LC123 tsiz2
        | | | | | | | | | | +----------- LC120 tt1
        | | | | | | | | | | | +--------- LC114 |601sim:1|601state:1|olap
        | | | | | | | | | | | | +------- LC119 |601sim:1|601state:1.split
        | | | | | | | | | | | | | +----- LC116 |601sim:1|601state:1|ta0
        | | | | | | | | | | | | | | +--- LC124 |601sim:1|601state:1|ta1
        | | | | | | | | | | | | | | | +- LC127 |601sim:1|601state:1|ta2
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC126-> - * * - * - - * * * * - - - - - | - - - - * - - * | <-- adr0
LC128-> * * * - * - - * * * * - - - - - | - - - - - - - * | <-- adr1
LC125-> - - - * - - - - - - - * - - - - | * - - - - - - * | <-- /dbb
LC118-> - - - - * - - - - - - - - * - * | * - - - - - - * | <-- /tbst
LC121-> - - - * - * - - - - - - - * * * | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~2
LC117-> - * * - - - * * * * * - - - - - | - - - - - - - * | <-- tsiz1
LC120-> - * * - * - - * * * * - - - - - | - - - - * - - * | <-- tt1
LC114-> - - - * - - - - - - - * - - - - | - - - - - - - * | <-- |601sim:1|601state:1|olap
LC119-> - * * - * - - * * * * - * - - * | - - - - * - - * | <-- |601sim:1|601state:1.split
LC116-> - - - - - - - - - - - - * * * * | - - - - - - - * | <-- |601sim:1|601state:1|ta0
LC124-> - - - * - - - - - - - - * * * * | - - - - - - - * | <-- |601sim:1|601state:1|ta1
LC127-> - - - * - - - - - - - - * * * * | - - - - - - - * | <-- |601sim:1|601state:1|ta2

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- pclk
84   -> - * * * * * - * * * * * * * * * | * * * * * * * * | <-- /reset
2    -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- 2xpclk
LC72 -> * - - - - * * - - - - - - - - - | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~1
LC76 -> * - - - - * * - - - - - - - - - | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~2
LC78 -> * - - - - * * - - - - - - - - - | * - - - * - - * | <-- |toplev:2|abus:127|addr_state~3
LC89 -> - - - * - * - - - - - - - * * * | - - - * - * * * | <-- |toplev:2|dbus:129|data_state~1
LC86 -> - - - - - * - - - - - - - - - - | - - - - - - * * | <-- |toplev:2|:181
LC33 -> - - - - - * - - - - - - - - - - | - - - - * * * * | <-- |toplev:2|:182
LC80 -> - - - * * - - - - - - * * - - - | - - - - * - - * | <-- /ts
LC79 -> - * * - * - - * * * * - * - - - | - - - - * - - * | <-- |601sim:1|601state:1|ABB


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    c:\bean\mb.rpt
mb

** EQUATIONS **

adr27    : INPUT;
adr28    : INPUT;
adr29    : INPUT;
adr30    : INPUT;
adr31    : INPUT;
pclk     : INPUT;
spdsel_0 : INPUT;
spdsel_1 : INPUT;
2xpclk   : INPUT;
/reset   : INPUT;

-- Node name is 'acia/cs' 
-- Equation name is 'acia/cs', location is LC056, type is output.
 acia/cs = LCELL( _EQ001 $  GND);
  _EQ001 =  _LC039 & !_LC059 & !_LC060 &  _LC108
         # !_LC039 & !_LC059 & !_LC060 & !_LC108
         # !_LC039 & !_LC060 &  _LC108;

-- Node name is 'addr_latch' 
-- Equation name is 'addr_latch', location is LC006, type is output.
 addr_latch = LCELL( _EQ002 $  GND);
  _EQ002 = !_LC072 &  _LC076 & !_LC078;

-- Node name is 'addr_out0' 
-- Equation name is 'addr_out0', location is LC064, type is output.
 addr_out0 = LCELL( _EQ003 $  _LC068);
  _EQ003 =  /cs_ram &  _LC063 & !_LC068 &  _LC113
         #  /cs_ram & !_LC063 &  _LC068 &  _LC113;

-- Node name is 'addr_out1' 
-- Equation name is 'addr_out1', location is LC061, type is output.
 addr_out1 = LCELL( _EQ004 $  _LC070);
  _EQ004 =  /cs_ram &  _LC054 & !_LC070 &  _LC113
         #  /cs_ram & !_LC054 &  _LC070 &  _LC113;

-- Node name is 'addr_out2' 
-- Equation name is 'addr_out2', location is LC096, type is output.
 addr_out2 = LCELL( _EQ005 $  _LC071);
  _EQ005 =  /cs_ram & !_LC071 &  _LC107 &  _LC113
         #  /cs_ram &  _LC071 & !_LC107 &  _LC113;

-- Node name is 'addr_out3' 
-- Equation name is 'addr_out3', location is LC085, type is output.
 addr_out3 = LCELL( _EQ006 $  GND);
  _EQ006 =  /cs_ram & !_LC010 &  _LC047 &  _LC113
         # !_LC010 &  _LC087 & !_LC113
         # !/cs_ram & !_LC010 &  _LC087
         #  _LC010 &  _LC069;

-- Node name is 'addr_out4' 
-- Equation name is 'addr_out4', location is LC094, type is output.
 addr_out4 = LCELL( _EQ007 $  _LC015);
  _EQ007 =  /cs_ram &  _LC034 &  _LC113
         # !/cs_ram &  _LC095
         #  _LC095 & !_LC113;

-- Node name is 'adr0' = '|601sim:1.A0' from file "601cycle.tdf" line 12, column 31
-- Equation name is 'adr0', type is output 
 adr0    = TFFE( _EQ008, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ008 = !adr1 & !_LC079 & !_LC119 & !tsiz1 &  tt1
         # !adr0 & !_LC079 & !_LC119 & !tsiz1
         # !adr0 & !tsiz1 &  tt1
         # !adr0 &  adr1;

-- Node name is 'adr1' = '|601sim:1.A1' from file "601cycle.tdf" line 12, column 35
-- Equation name is 'adr1', type is output 
 adr1    = TFFE( _EQ009, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ009 =  adr0 & !_LC079 & !_LC119 &  tsiz1 &  tt1
         # !adr0 & !adr1 & !_LC079 & !_LC119 & !tsiz1
         # !adr0 & !adr1 & !tsiz1 &  tt1
         #  adr0 & !adr1 &  tsiz1;

-- Node name is 'byte_lane0' 
-- Equation name is 'byte_lane0', location is LC043, type is output.
 byte_lane0 = LCELL( _EQ010 $  VCC);
  _EQ010 = !_LC104 & !_LC111 &  _X001;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);

-- Node name is 'byte_lane1' 
-- Equation name is 'byte_lane1', location is LC038, type is output.
 byte_lane1 = LCELL( _EQ011 $  VCC);
  _EQ011 = !_LC100 & !_LC104 &  _X001;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);

-- Node name is 'byte_lane2' 
-- Equation name is 'byte_lane2', location is LC035, type is output.
 byte_lane2 = LCELL( _EQ012 $  VCC);
  _EQ012 = !_LC104 & !_LC109 &  _X001;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);

-- Node name is 'byte_lane3' 
-- Equation name is 'byte_lane3', location is LC045, type is output.
 byte_lane3 = LCELL( _EQ013 $  VCC);
  _EQ013 = !_LC104 & !_LC110 &  _X001;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);

-- Node name is 'byte_lane4' 
-- Equation name is 'byte_lane4', location is LC048, type is output.
 byte_lane4 = LCELL( _EQ014 $  VCC);
  _EQ014 = !_LC104 & !_LC106 &  _X001;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);

-- Node name is 'byte_lane5' 
-- Equation name is 'byte_lane5', location is LC037, type is output.
 byte_lane5 = LCELL( _EQ015 $  VCC);
  _EQ015 = !_LC036 & !_LC104 &  _X001;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);

-- Node name is 'byte_lane6' 
-- Equation name is 'byte_lane6', location is LC046, type is output.
 byte_lane6 = LCELL( _EQ016 $  VCC);
  _EQ016 = !_LC104 &  _X001 &  _X002 &  _X003 &  _X004 &  _X005;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);
  _X002  = EXP(!_LC039 &  _LC054 & !_LC059 &  _LC060 & !_LC063 &  _LC107 & 
              _LC108 &  LTT1);
  _X003  = EXP(!_LC028 &  _LC054 & !_LC057 & !_LC063 &  _LC098 &  _LC103 & 
              _LC107 &  LTT1);
  _X004  = EXP( _LC050 &  _LC054 & !_LC063 & !_LC066 &  _LC081 & !_LC082 & 
              _LC107 &  LTT1);
  _X005  = EXP(!_LC039 &  _LC054 &  _LC059 & !_LC060 & !_LC063 &  _LC107 & 
             !_LC108 &  LTT1);

-- Node name is 'byte_lane7' 
-- Equation name is 'byte_lane7', location is LC040, type is output.
 byte_lane7 = LCELL( _EQ017 $  VCC);
  _EQ017 = !_LC104 &  _X001 &  _X006 &  _X007 &  _X008 &  _X009;
  _X001  = EXP(!/cs_ram & !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & 
             !_LC098 & !_LC103 & !_LC108 &  LTT1);
  _X006  = EXP(!_LC039 &  _LC054 & !_LC059 &  _LC060 &  _LC063 &  _LC107 & 
              _LC108 &  LTT1);
  _X007  = EXP(!_LC028 &  _LC054 & !_LC057 &  _LC063 &  _LC098 &  _LC103 & 
              _LC107 &  LTT1);
  _X008  = EXP( _LC050 &  _LC054 &  _LC063 & !_LC066 &  _LC081 & !_LC082 & 
              _LC107 &  LTT1);
  _X009  = EXP(!_LC039 &  _LC054 &  _LC059 & !_LC060 &  _LC063 &  _LC107 & 
             !_LC108 &  LTT1);

-- Node name is 'c/r_mux' 
-- Equation name is 'c/r_mux', location is LC051, type is output.
 c/r_mux = LCELL( _EQ018 $  GND);
  _EQ018 =  _LC081 & !_LC082;

-- Node name is 'e_clock' = '|toplev:2.E_CLOCK' from file "io.tdf" line 27, column 2
-- Equation name is 'e_clock', type is output 
 e_clock = TFFE( _EQ019, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ019 = !_LC019 & !_LC021 & !_LC029 & !_LC030;

-- Node name is 'LTT1' = '|toplev:2.LTT1' 
-- Equation name is 'LTT1', type is output 
 LTT1    = DFFE( tt1 $  GND,  _EQ020,  VCC,  VCC,  VCC);
  _EQ020 = !_LC072 &  _LC076 & !_LC078;

-- Node name is 'tsiz0' = '|601sim:1.TSIZ2' from file "601cycle.tdf" line 31, column 9
-- Equation name is 'tsiz0', type is output 
 tsiz0   = DFFE( _EQ021 $  GND, GLOBAL( pclk),  VCC,  VCC,  VCC);
  _EQ021 =  adr0 &  adr1 & !_LC079 & !_LC119 &  /reset &  tsiz1 &  tt1
         # !adr0 & !adr1 & !_LC079 & !_LC119 &  /reset &  tsiz1 &  tt1
         #  adr0 & !adr1 &  /reset & !tsiz1 &  tt1 &  _X010
         # !adr0 & !adr1 &  /reset & !tsiz1 & !tt1 &  _X010
         #  adr0 & !adr1 &  /reset & !tsiz1 & !tt1;
  _X010  = EXP(!_LC079 & !_LC119);

-- Node name is 'tsiz1' = '|601sim:1.TSIZ1' from file "601cycle.tdf" line 12, column 44
-- Equation name is 'tsiz1', type is output 
 tsiz1   = DFFE( _EQ022 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ022 =  adr0 &  adr1 &  tsiz1 &  tt1 &  _X010
         #  adr0 & !_LC079 & !_LC119 & !tsiz1 &  tt1
         # !adr0 & !adr1 &  tsiz1 &  _X011;
  _X010  = EXP(!_LC079 & !_LC119);
  _X011  = EXP(!_LC079 & !_LC119 &  tt1);

-- Node name is 'tsiz2' = '|601sim:1.TSIZ0' from file "601cycle.tdf" line 31, column 2
-- Equation name is 'tsiz2', type is output 
 tsiz2   = DFFE( _EQ023 $ !/reset, GLOBAL( pclk),  VCC,  VCC,  VCC);
  _EQ023 =  adr0 &  adr1 &  _LC119 &  /reset & !tsiz1 &  tt1
         #  adr0 &  adr1 &  _LC079 &  /reset & !tsiz1 &  tt1
         # !adr0 & !adr1 & !_LC079 & !_LC119 &  /reset & !tsiz1;

-- Node name is 'tt1' = '|601sim:1.TT1' from file "601cycle.tdf" line 12, column 39
-- Equation name is 'tt1', type is output 
 tt1     = DFFE( _EQ024 $  VCC, GLOBAL( pclk),  VCC,  /reset,  VCC);
  _EQ024 =  adr0 &  adr1 & !_LC079 & !_LC119 &  tsiz1 &  tt1
         # !adr0 & !adr1 & !_LC079 & !_LC119 &  tsiz1 &  tt1
         #  adr0 & !adr1 & !_LC079 & !_LC119 & !tsiz1 &  tt1
         # !adr1 & !tt1 &  _X010 &  _X012;
  _X010  = EXP(!_LC079 & !_LC119);
  _X012  = EXP( adr0 &  tsiz1);

-- Node name is '|adrlatch:7|74374:1|:16' 
-- Equation name is '_LC015', type is buried 
_LC015   = DFFE( adr27 $  GND,  _EQ025,  VCC,  VCC,  VCC);
  _EQ025 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|adrlatch:7|74374:1|:17' 
-- Equation name is '_LC069', type is buried 
_LC069   = DFFE( adr28 $  GND,  _EQ026,  VCC,  VCC,  VCC);
  _EQ026 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|adrlatch:7|74374:1|:18' 
-- Equation name is '_LC071', type is buried 
_LC071   = DFFE( adr29 $  GND,  _EQ027,  VCC,  VCC,  VCC);
  _EQ027 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|adrlatch:7|74374:1|:19' 
-- Equation name is '_LC070', type is buried 
_LC070   = DFFE( adr30 $  GND,  _EQ028,  VCC,  VCC,  VCC);
  _EQ028 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|adrlatch:7|74374:1|:20' 
-- Equation name is '_LC068', type is buried 
_LC068   = DFFE( adr31 $  GND,  _EQ029,  VCC,  VCC,  VCC);
  _EQ029 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|adrlatch:7|74374:3|:14' 
-- Equation name is '_LC113', type is buried 
_LC113   = DFFE( adr1 $  GND,  _EQ030,  VCC,  VCC,  VCC);
  _EQ030 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|toplev:2|abus:127|addr_state~1' from file "abus.tdf" line 15, column 2
-- Equation name is '_LC072', type is buried 
_LC072   = TFFE( _EQ031, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ031 =  _LC033 &  _LC072 & !_LC078 &  /ts
         #  _LC072 &  _LC076
         #  _LC076 & !_LC078;

-- Node name is '|toplev:2|abus:127|addr_state~2' from file "abus.tdf" line 15, column 2
-- Equation name is '_LC076', type is buried 
_LC076   = DFFE( _EQ032 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ032 =  _LC033 &  _LC072 & !_LC076 &  _LC078
         #  _LC033 & !_LC076 & !_LC078 & !/ts
         # !_LC072 & !_LC076 & !_LC078 & !/ts
         #  _LC072 &  _LC076 & !_LC078;

-- Node name is '|toplev:2|abus:127|addr_state~3' from file "abus.tdf" line 15, column 2
-- Equation name is '_LC078', type is buried 
_LC078   = DFFE( _EQ033 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ033 = !_LC033 &  _LC072 & !_LC076 & !/ts
         # !_LC033 &  _LC072 & !_LC076 &  _LC078;

-- Node name is '|toplev:2|8and:200|~51~1' = '|toplev~2.BYTE_LANE0~1' from file "8and.tdf" line 17, column 32
-- Equation name is '_LC104', type is buried 
-- synthesized logic cell 
_LC104   = LCELL( _EQ034 $  GND);
  _EQ034 = !_LC028 & !_LC039 & !_LC057 & !_LC059 &  _LC060 & !_LC098 & 
             !_LC103 &  _LC108 & !_LC113 &  LTT1
         # !/cs_ram & !_LC028 & !_LC039 & !_LC057 & !_LC059 &  _LC060 & 
             !_LC098 & !_LC103 &  _LC108 &  LTT1
         # !_LC028 &  _LC050 & !_LC057 & !_LC066 &  _LC081 & !_LC082 & 
             !_LC098 & !_LC103 & !_LC113 &  LTT1
         # !/cs_ram & !_LC028 &  _LC050 & !_LC057 & !_LC066 &  _LC081 & 
             !_LC082 & !_LC098 & !_LC103 &  LTT1
         # !_LC028 & !_LC039 & !_LC057 &  _LC059 & !_LC060 & !_LC098 & 
             !_LC103 & !_LC108 & !_LC113 &  LTT1;

-- Node name is '|toplev:2|8and:200|~51~2' = '|toplev~2.BYTE_LANE0~2' from file "8and.tdf" line 17, column 32
-- Equation name is '_LC111', type is buried 
-- synthesized logic cell 
_LC111   = LCELL( _EQ035 $  GND);
  _EQ035 = !_LC039 & !_LC054 & !_LC059 &  _LC060 & !_LC063 & !_LC107 & 
              _LC108 &  LTT1
         # !_LC028 & !_LC054 & !_LC057 & !_LC063 &  _LC098 &  _LC103 & 
             !_LC107 &  LTT1
         #  _LC050 & !_LC054 & !_LC063 & !_LC066 &  _LC081 & !_LC082 & 
             !_LC107 &  LTT1
         # !_LC039 & !_LC054 &  _LC059 & !_LC060 & !_LC063 & !_LC107 & 
             !_LC108 &  LTT1;

-- Node name is '|toplev:2|8and:200|~50~1' = '|toplev~2.BYTE_LANE1~1' from file "8and.tdf" line 16, column 32
-- Equation name is '_LC100', type is buried 
-- synthesized logic cell 
_LC100   = LCELL( _EQ036 $  GND);
  _EQ036 = !_LC039 & !_LC054 & !_LC059 &  _LC060 &  _LC063 & !_LC107 & 
              _LC108 &  LTT1
         # !_LC028 & !_LC054 & !_LC057 &  _LC063 &  _LC098 &  _LC103 & 
             !_LC107 &  LTT1
         #  _LC050 & !_LC054 &  _LC063 & !_LC066 &  _LC081 & !_LC082 & 
             !_LC107 &  LTT1
         # !_LC039 & !_LC054 &  _LC059 & !_LC060 &  _LC063 & !_LC107 & 
             !_LC108 &  LTT1;

-- Node name is '|toplev:2|8and:200|~49~1' = '|toplev~2.BYTE_LANE2~1' from file "8and.tdf" line 15, column 32
-- Equation name is '_LC109', type is buried 
-- synthesized logic cell 
_LC109   = LCELL( _EQ037 $  GND);
  _EQ037 = !_LC039 &  _LC054 & !_LC059 &  _LC060 & !_LC063 & !_LC107 & 
              _LC108 &  LTT1
         # !_LC028 &  _LC054 & !_LC057 & !_LC063 &  _LC098 &  _LC103 & 
             !_LC107 &  LTT1
         #  _LC050 &  _LC054 & !_LC063 & !_LC066 &  _LC081 & !_LC082 & 
             !_LC107 &  LTT1
         # !_LC039 &  _LC054 &  _LC059 & !_LC060 & !_LC063 & !_LC107 & 
             !_LC108 &  LTT1;

-- Node name is '|toplev:2|8and:200|~48~1' = '|toplev~2.BYTE_LANE3~1' from file "8and.tdf" line 14, column 32
-- Equation name is '_LC110', type is buried 
-- synthesized logic cell 
_LC110   = LCELL( _EQ038 $  GND);
  _EQ038 = !_LC039 &  _LC054 & !_LC059 &  _LC060 &  _LC063 & !_LC107 & 
              _LC108 &  LTT1
         # !_LC028 &  _LC054 & !_LC057 &  _LC063 &  _LC098 &  _LC103 & 
             !_LC107 &  LTT1
         #  _LC050 &  _LC054 &  _LC063 & !_LC066 &  _LC081 & !_LC082 & 
             !_LC107 &  LTT1
         # !_LC039 &  _LC054 &  _LC059 & !_LC060 &  _LC063 & !_LC107 & 
             !_LC108 &  LTT1;

-- Node name is '|toplev:2|8and:200|~47~1' = '|toplev~2.BYTE_LANE4~1' from file "8and.tdf" line 13, column 32
-- Equation name is '_LC106', type is buried 
-- synthesized logic cell 
_LC106   = LCELL( _EQ039 $  GND);
  _EQ039 = !_LC039 & !_LC054 & !_LC059 &  _LC060 & !_LC063 &  _LC107 & 
              _LC108 &  LTT1
         # !_LC028 & !_LC054 & !_LC057 & !_LC063 &  _LC098 &  _LC103 & 
              _LC107 &  LTT1
         #  _LC050 & !_LC054 & !_LC063 & !_LC066 &  _LC081 & !_LC082 & 
              _LC107 &  LTT1
         # !_LC039 & !_LC054 &  _LC059 & !_LC060 & !_LC063 &  _LC107 & 
             !_LC108 &  LTT1;

-- Node name is '|toplev:2|8and:200|~46~1' = '|toplev~2.BYTE_LANE5~1' from file "8and.tdf" line 12, column 32
-- Equation name is '_LC036', type is buried 
-- synthesized logic cell 
_LC036   = LCELL( _EQ040 $  GND);
  _EQ040 = !_LC039 & !_LC054 & !_LC059 &  _LC060 &  _LC063 &  _LC107 & 
              _LC108 &  LTT1
         # !_LC028 & !_LC054 & !_LC057 &  _LC063 &  _LC098 &  _LC103 & 
              _LC107 &  LTT1
         #  _LC050 & !_LC054 &  _LC063 & !_LC066 &  _LC081 & !_LC082 & 
              _LC107 &  LTT1
         # !_LC039 & !_LC054 &  _LC059 & !_LC060 &  _LC063 &  _LC107 & 
             !_LC108 &  LTT1;

-- Node name is '|toplev:2|ram:132|~137~1' = '|toplev~2./CAS4~1' from file "ram.tdf" line 43, column 13
-- Equation name is '_LC001', type is buried 
-- synthesized logic cell 
_LC001   = LCELL( _EQ041 $  GND);
  _EQ041 =  _LC042 & !_LC068 & !_LC071 & !_LC073 &  _LC074 &  _LC122
         #  _LC042 &  _LC068 & !_LC070 & !_LC071 & !_LC074 &  _LC122
         #  _LC042 &  _LC068 & !_LC070 & !_LC071 &  _LC073 & !_LC074
         #  _LC042 & !_LC068 &  _LC073 &  _LC074 & !_LC122
         #  _LC042 & !_LC068 &  _LC071 &  _LC074 & !_LC122;

-- Node name is '|toplev:2|ram:132|~139~1' = '|toplev~2./CAS6~1' from file "ram.tdf" line 43, column 13
-- Equation name is '_LC102', type is buried 
-- synthesized logic cell 
_LC102   = LCELL( _EQ042 $  GND);
  _EQ042 =  _LC010 &  _LC042 & !_LC068 &  _LC070 & !_LC071 & !_LC073 & 
              _LC074 & !_LC091 &  _LC122
         #  _LC010 &  _LC042 &  _LC068 & !_LC070 & !_LC071 & !_LC073 & 
              _LC074 & !_LC091 & !_LC122
         #  _LC010 &  _LC042 & !_LC068 & !_LC070 & !_LC071 & !_LC073 & 
             !_LC074 & !_LC091 & !_LC122
         # !_LC010 &  _LC042 & !_LC091;

-- Node name is '|toplev:2|dbus:129|data_state~1' from file "dbus.tdf" line 16, column 2
-- Equation name is '_LC089', type is buried 
_LC089   = TFFE( _EQ043, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ043 = !_LC089 &  _LC097 &  _LC121
         #  _LC033 &  _LC089 & !_LC121;

-- Node name is '|toplev:2|dbus:129|data_state~2' from file "dbus.tdf" line 16, column 2
-- Equation name is '_LC121', type is buried 
_LC121   = TFFE( _EQ044, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ044 = !_LC072 &  _LC076 & !_LC078 & !_LC089 & !_LC121
         #  _LC086 &  _LC089 &  _LC121
         # !_LC033 &  _LC089 & !_LC121;

-- Node name is '|toplev:2|io:162|E_clock~1' from file "io.tdf" line 23, column 2
-- Equation name is '_LC021', type is buried 
_LC021   = DFFE( _EQ045 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ045 = !_LC019 & !_LC021 &  _LC029 & !_LC030
         # !_LC021 & !_LC029 &  _LC030
         #  _LC019 & !_LC021 & !_LC029;

-- Node name is '|toplev:2|io:162|E_clock~2' from file "io.tdf" line 23, column 2
-- Equation name is '_LC019', type is buried 
_LC019   = DFFE( _EQ046 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ046 = !_LC019 & !_LC021 & !_LC029 &  _LC030
         # !_LC019 & !_LC021 &  _LC029 & !_LC030
         #  _LC019 &  _LC021 & !_LC029;

-- Node name is '|toplev:2|io:162|E_clock~3' from file "io.tdf" line 23, column 2
-- Equation name is '_LC030', type is buried 
_LC030   = TFFE( _EQ047, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ047 = !_LC019 & !_LC021 &  _LC030
         # !_LC019 & !_LC021 &  _LC029
         #  _LC029 &  _LC030;

-- Node name is '|toplev:2|io:162|E_clock~4' from file "io.tdf" line 23, column 2
-- Equation name is '_LC029', type is buried 
_LC029   = DFFE( _EQ048 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ048 = !_LC019 & !_LC021 & !_LC029 & !_LC030;

-- Node name is '|toplev:2|io:162|io_state~1' from file "io.tdf" line 18, column 2
-- Equation name is '_LC060', type is buried 
_LC060   = DFFE( _EQ049 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ049 =  _LC059 & !_LC060 & !_LC108 &  spdsel_0 &  spdsel_1
         #  _LC039 & !_LC059 &  _LC060 &  _LC108
         # !_LC039 &  _LC059;

-- Node name is '|toplev:2|io:162|io_state~2' from file "io.tdf" line 18, column 2
-- Equation name is '_LC059', type is buried 
_LC059   = DFFE( _EQ050 $  GND, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ050 = !e_clock & !_LC039 &  _LC108 &  _X013
         #  _LC059 & !_LC108 &  _X014
         #  _LC039 & !_LC060 & !_LC108
         # !_LC039 &  _LC059 & !_LC060;
  _X013  = EXP(!_LC059 &  _LC060);
  _X014  = EXP(!e_clock & !_LC039);

-- Node name is '|toplev:2|io:162|io_state~3~1' from file "io.tdf" line 18, column 2
-- Equation name is '_LC062', type is buried 
-- synthesized logic cell 
_LC062   = LCELL( _EQ051 $  GND);
  _EQ051 =  e_clock & !_LC039 &  _LC059 &  _LC060 &  _LC108
         #  /cs_ram & !_LC039 & !_LC059 & !_LC060 & !_LC089 & !_LC108 & 
             !_LC113 &  _LC121
         # !e_clock &  _LC039 & !_LC059 & !_LC060 &  _LC108
         #  _LC039 & !_LC059 &  _LC060 & !_LC108
         #  _LC039 & !_LC060 & !_LC108 &  spdsel_0 &  spdsel_1;

-- Node name is '|toplev:2|io:162|io_state~3' from file "io.tdf" line 18, column 2
-- Equation name is '_LC039', type is buried 
_LC039   = DFFE( _EQ052 $  VCC, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ052 = !_LC062 &  _X015 &  _X016 &  _X017;
  _X015  = EXP( _LC039 & !_LC059 &  _LC060 &  LTT1);
  _X016  = EXP( e_clock &  _LC039 & !_LC059 &  _LC060);
  _X017  = EXP( _LC039 & !_LC059 & !_LC108 &  spdsel_1);

-- Node name is '|toplev:2|io:162|io_state~4' from file "io.tdf" line 18, column 2
-- Equation name is '_LC108', type is buried 
_LC108   = TFFE( _EQ053, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ053 =  /cs_ram & !_LC039 & !_LC059 & !_LC060 & !_LC089 & !_LC108 & 
             !_LC113 &  _LC121
         # !_LC059 &  _LC060 &  _LC108 &  LTT1
         # !_LC039 & !_LC059 &  _LC060 &  _LC108
         #  _LC039 &  _LC059 &  _LC108;

-- Node name is '|toplev:2|~196~1' = '|toplev:2|LTSIZ0' 
-- Equation name is '_LC073', type is buried 
_LC073   = DFFE( tsiz0 $  GND,  _EQ054,  VCC,  VCC,  VCC);
  _EQ054 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|toplev:2|~196~2' = '|toplev:2|LTSIZ1' 
-- Equation name is '_LC122', type is buried 
_LC122   = DFFE( tsiz1 $  GND,  _EQ055,  VCC,  VCC,  VCC);
  _EQ055 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|toplev:2|~196~3' = '|toplev:2|LTSIZ2' 
-- Equation name is '_LC074', type is buried 
_LC074   = DFFE( tsiz2 $  GND,  _EQ056,  VCC,  VCC,  VCC);
  _EQ056 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|toplev:2|ram:132|B_COUNT0' = '|toplev:2|ram:132.ao3' from file "ram.tdf" line 36, column 9
-- Equation name is '_LC087', type is buried 
_LC087   = DFFE( _EQ057 $  GND, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ057 = !_LC010 &  _LC050 & !_LC066 &  _LC081 & !_LC082 & !_LC087
         # !_LC050 & !_LC066 &  _LC081 & !_LC082 &  _LC087
         #  _LC066 &  _LC081 & !_LC082 &  _LC087;

-- Node name is '|toplev:2|ram:132|B_COUNT1' from file "ram.tdf" line 36, column 9
-- Equation name is '_LC095', type is buried 
_LC095   = DFFE( _EQ058 $  GND, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ058 = !_LC010 &  _LC050 & !_LC066 &  _LC081 & !_LC082 &  _LC087 & 
             !_LC095
         # !_LC010 &  _LC050 & !_LC066 &  _LC081 & !_LC082 & !_LC087 & 
              _LC095
         # !_LC050 & !_LC066 &  _LC081 & !_LC082 &  _LC095
         #  _LC066 &  _LC081 & !_LC082 &  _LC095;

-- Node name is '|toplev:2|ram:132|CAS_FF' from file "ram.tdf" line 34, column 10
-- Equation name is '_LC042', type is buried 
_LC042   = DFFE( _EQ059 $  GND, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ059 =  _LC050 &  _LC066 & !_LC081 &  _LC082
         # !_LC050 &  _LC066 &  _LC081 & !_LC082
         # !_LC050 & !_LC066 &  _LC081;

-- Node name is '|toplev:2|ram:132|ram_state~1' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC066', type is buried 
_LC066   = DFFE( _EQ060 $  _EQ061, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ060 = !_LC066 &  _LC081 & !_LC082 &  _LC087 &  _LC095 &  _X018 &  _X019 & 
              _X020 &  _X021 &  _X022
         # !_LC066 & !_LC081 &  _LC082 &  spdsel_0 & !spdsel_1 &  _X018 & 
              _X019 &  _X020 &  _X021 &  _X022
         # !_LC066 & !_LC081 &  _LC082 & !spdsel_0 &  spdsel_1 &  _X018 & 
              _X019 &  _X020 &  _X021 &  _X022;
  _X018  = EXP( _LC010 & !_LC066 &  _LC081 & !_LC082);
  _X019  = EXP( _LC050 &  _LC066 &  _LC081 &  _LC082);
  _X020  = EXP( _LC066 & !_LC081 & !_LC082);
  _X021  = EXP(!_LC050 & !_LC081);
  _X022  = EXP(!_LC050 & !_LC082);
  _EQ061 =  _X018 &  _X019 &  _X020 &  _X021 &  _X022;
  _X018  = EXP( _LC010 & !_LC066 &  _LC081 & !_LC082);
  _X019  = EXP( _LC050 &  _LC066 &  _LC081 &  _LC082);
  _X020  = EXP( _LC066 & !_LC081 & !_LC082);
  _X021  = EXP(!_LC050 & !_LC081);
  _X022  = EXP(!_LC050 & !_LC082);

-- Node name is '|toplev:2|ram:132|ram_state~2' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC050', type is buried 
_LC050   = DFFE( _EQ062 $  _EQ063, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ062 = !_LC012 & !_LC016 & !_LC018 & !_LC022 & !_LC026 & !_LC049 & 
             !_LC052 & !_LC066 & !_LC081 & !_LC082 & !_LC090 & !_LC092
         # !_LC066 & !_LC081 & !_LC082 &  _X023;
  _X023  = EXP(!/cs_ram & !_LC050 & !_LC089 &  _LC121);
  _EQ063 =  _X024 &  _X025 &  _X026 &  _X027;
  _X024  = EXP( _LC066 &  _LC081 & !_LC082);
  _X025  = EXP( _LC050 &  _LC081 &  _LC082);
  _X026  = EXP( _LC066 & !_LC081 &  _LC082);
  _X027  = EXP(!_LC050 &  _LC066 & !_LC081);

-- Node name is '|toplev:2|ram:132|ram_state~3' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC082', type is buried 
_LC082   = TFFE(!_EQ064, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ064 =  _X028 &  _X029 &  _X030 &  _X031 &  _X032;
  _X028  = EXP( _LC066 &  _LC081 &  _LC082);
  _X029  = EXP(!_LC012 & !_LC016 & !_LC018 & !_LC022 & !_LC026 & !_LC049 & 
             !_LC050 & !_LC052 & !_LC066 & !_LC081 & !_LC082 & !_LC090 & 
             !_LC092);
  _X030  = EXP(!/cs_ram & !_LC050 & !_LC066 & !_LC081 & !_LC082 & !_LC089 & 
              _LC121);
  _X031  = EXP( _LC050 & !_LC066 & !_LC081 &  _LC082);
  _X032  = EXP(!_LC066 & !_LC081 &  _LC082 & !spdsel_0 & !spdsel_1);

-- Node name is '|toplev:2|ram:132|ram_state~4' from file "ram.tdf" line 25, column 2
-- Equation name is '_LC081', type is buried 
_LC081   = TFFE(!_EQ065, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ065 =  _X019 &  _X029 &  _X030 &  _X033 &  _X034 &  _X035;
  _X019  = EXP( _LC050 &  _LC066 &  _LC081 &  _LC082);
  _X029  = EXP(!_LC012 & !_LC016 & !_LC018 & !_LC022 & !_LC026 & !_LC049 & 
             !_LC050 & !_LC052 & !_LC066 & !_LC081 & !_LC082 & !_LC090 & 
             !_LC092);
  _X030  = EXP(!/cs_ram & !_LC050 & !_LC066 & !_LC081 & !_LC082 & !_LC089 & 
              _LC121);
  _X033  = EXP( _LC050 & !_LC066 &  _LC081 & !_LC082 &  _LC087 &  _LC095);
  _X034  = EXP( _LC010 &  _LC050 & !_LC066 &  _LC081 & !_LC082);
  _X035  = EXP(!_LC050 & !_LC066 &  _LC081 &  _LC082);

-- Node name is '|toplev:2|ram:132|R_COUNT0' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC049', type is buried 
_LC049   = TFFE(!_EQ066, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ066 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 &  _LC049 & 
              _LC052 &  _LC090 &  _LC092 &  spdsel_0 &  spdsel_1 &  _X036
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 & !_LC049 & 
             !_LC052 &  _LC090 & !_LC092 & !spdsel_0 &  spdsel_1
         # !_LC012 & !_LC016 & !_LC018 &  _LC022 &  _LC026 & !_LC049 & 
             !_LC052 &  _LC090 & !_LC092 &  spdsel_0 & !spdsel_1
         # !_LC012 &  _LC016 & !_LC018 & !_LC022 &  _LC026 & !_LC049 & 
             !_LC052 & !_LC090 & !_LC092 & !spdsel_0 & !spdsel_1;
  _X036  = EXP(!_LC050 & !_LC066 & !_LC081 & !_LC082);

-- Node name is '|toplev:2|ram:132|R_COUNT1' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC092', type is buried 
_LC092   = DFFE( _EQ067 $ !_LC049, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ067 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 &  _LC049 & 
              _LC052 &  _LC090 &  spdsel_0 &  spdsel_1 &  _X036
         # !_LC092;
  _X036  = EXP(!_LC050 & !_LC066 & !_LC081 & !_LC082);

-- Node name is '|toplev:2|ram:132|R_COUNT2' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC018', type is buried 
_LC018   = DFFE( _EQ068 $  VCC, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ068 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 & !_LC049 & 
             !_LC050 & !_LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC090 & 
             !_LC092 & !spdsel_0 &  spdsel_1
         #  _LC018 &  _LC049 & !_LC050 & !_LC066 & !_LC081 & !_LC082 & 
              _LC092
         #  _LC018 &  _LC049 &  _LC092 &  _X037
         # !_LC018 &  _X038;
  _X037  = EXP( _LC012 &  _LC016 &  _LC022 &  _LC026 &  _LC052 &  _LC090 & 
              spdsel_0 &  spdsel_1);
  _X038  = EXP( _LC049 &  _LC092);

-- Node name is '|toplev:2|ram:132|R_COUNT3' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC052', type is buried 
_LC052   = DFFE( _EQ069 $  VCC, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ069 =  _LC018 &  _LC049 & !_LC050 &  _LC052 & !_LC066 & !_LC081 & 
             !_LC082 &  _LC092
         #  _LC018 &  _LC049 &  _LC052 &  _LC092 &  _X039
         # !_LC052 &  _X040;
  _X039  = EXP( _LC012 &  _LC016 &  _LC022 &  _LC026 &  _LC090 &  spdsel_0 & 
              spdsel_1);
  _X040  = EXP( _LC018 &  _LC049 &  _LC092);

-- Node name is '|toplev:2|ram:132|R_COUNT4' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC022', type is buried 
_LC022   = DFFE( _EQ070 $  _EQ071, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ070 =  _LC018 &  _LC022 &  _LC049 & !_LC050 &  _LC052 & !_LC066 & 
             !_LC081 & !_LC082 &  _LC092
         #  _LC018 &  _LC022 &  _LC049 &  _LC052 &  _LC092 &  _X041;
  _X041  = EXP( _LC012 &  _LC016 &  _LC026 &  _LC090 &  spdsel_0 &  spdsel_1);
  _EQ071 = !_LC017 &  _X042;
  _X042  = EXP(!_LC022 & !_LC049);

-- Node name is '|toplev:2|ram:132|R_COUNT5' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC012', type is buried 
_LC012   = TFFE( _EQ072, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ072 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 & !_LC049 & 
             !_LC050 & !_LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC090 & 
             !_LC092 & !spdsel_0 &  spdsel_1
         #  _LC012 &  _LC018 &  _LC022 &  _LC049 & !_LC050 &  _LC052 & 
             !_LC066 & !_LC081 & !_LC082 &  _LC092
         #  _LC012 &  _LC018 &  _LC022 &  _LC049 &  _LC052 &  _LC092 &  _X043
         # !_LC012 &  _LC018 &  _LC022 &  _LC049 &  _LC052 &  _LC092;
  _X043  = EXP( _LC016 &  _LC026 &  _LC090 &  spdsel_0 &  spdsel_1);

-- Node name is '|toplev:2|ram:132|R_COUNT6' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC016', type is buried 
_LC016   = DFFE( _EQ073 $ !_LC027, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ073 =  _LC012 &  _LC018 &  _LC022 &  _LC026 & !_LC049 & !_LC050 & 
             !_LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC090 & !_LC092 & 
             !spdsel_0 &  spdsel_1
         # !_LC012 & !_LC018 & !_LC022 &  _LC026 & !_LC049 & !_LC050 & 
             !_LC052 & !_LC066 & !_LC081 & !_LC082 & !_LC090 & !_LC092 & 
             !spdsel_0 & !spdsel_1
         # !_LC016 &  _X044;
  _X044  = EXP( _LC012 &  _LC018 &  _LC022 &  _LC049 &  _LC052 &  _LC092);

-- Node name is '|toplev:2|ram:132|R_COUNT7' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC090', type is buried 
_LC090   = DFFE( _EQ074 $ !_LC020, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ074 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 & !_LC049 & 
             !_LC050 & !_LC052 & !_LC066 & !_LC081 & !_LC082 & !_LC092 & 
             !spdsel_0 &  spdsel_1
         # !_LC012 & !_LC016 & !_LC018 &  _LC022 &  _LC026 & !_LC049 & 
             !_LC050 & !_LC052 & !_LC066 & !_LC081 & !_LC082 & !_LC092 & 
              spdsel_0 & !spdsel_1
         # !_LC090 &  _X045;
  _X045  = EXP( _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 &  _LC052 & 
              _LC092);

-- Node name is '|toplev:2|ram:132|R_COUNT8' from file "ram.tdf" line 35, column 9
-- Equation name is '_LC026', type is buried 
_LC026   = DFFE( _EQ075 $  _EQ076, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ075 = !_LC007 &  _LC012 &  _LC016 &  _LC018 &  _LC022 & !_LC025 & 
              _LC026 & !_LC049 & !_LC050 & !_LC052 & !_LC066 & !_LC081 & 
             !_LC082 &  _LC090 & !_LC092 & !spdsel_0 &  spdsel_1 &  _X046
         # !_LC007 & !_LC012 & !_LC016 & !_LC018 &  _LC022 & !_LC025 & 
              _LC026 & !_LC049 & !_LC050 & !_LC052 & !_LC066 & !_LC081 & 
             !_LC082 &  _LC090 & !_LC092 &  spdsel_0 & !spdsel_1 &  _X046
         # !_LC007 & !_LC012 &  _LC016 & !_LC018 & !_LC022 & !_LC025 & 
              _LC026 & !_LC049 & !_LC050 & !_LC052 & !_LC066 & !_LC081 & 
             !_LC082 & !_LC090 & !_LC092 & !spdsel_0 & !spdsel_1 &  _X046;
  _X046  = EXP(!_LC026 & !_LC049);
  _EQ076 = !_LC007 & !_LC025 &  _X046;
  _X046  = EXP(!_LC026 & !_LC049);

-- Node name is '|toplev:2|ram:132|~287~1' from file "ram.tdf" line 90, column 16
-- Equation name is '_LC017', type is buried 
-- synthesized logic cell 
_LC017   = LCELL( _EQ077 $  GND);
  _EQ077 =  _LC012 &  _LC016 &  _LC018 &  _LC026 & !_LC049 & !_LC050 & 
             !_LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC090 & !_LC092 & 
             !spdsel_0 &  spdsel_1
         # !_LC012 & !_LC016 & !_LC018 &  _LC026 & !_LC049 & !_LC050 & 
             !_LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC090 & !_LC092 & 
              spdsel_0 & !spdsel_1
         # !_LC022 & !_LC052
         # !_LC018 & !_LC022
         # !_LC022 & !_LC092;

-- Node name is '|toplev:2|ram:132|~293~1' from file "ram.tdf" line 90, column 16
-- Equation name is '_LC027', type is buried 
-- synthesized logic cell 
_LC027   = LCELL( _EQ078 $  GND);
  _EQ078 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 & !_LC050 & 
              _LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC092
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 &  _LC052 & 
              _LC092 & !spdsel_0
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 &  _LC052 & 
             !_LC090 &  _LC092
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 &  _LC052 & 
              _LC092 & !spdsel_1
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 & !_LC026 &  _LC049 & 
              _LC052 &  _LC092;

-- Node name is '|toplev:2|ram:132|~296~1' from file "ram.tdf" line 90, column 16
-- Equation name is '_LC020', type is buried 
-- synthesized logic cell 
_LC020   = LCELL( _EQ079 $  GND);
  _EQ079 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 & !_LC050 & 
              _LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC090 &  _LC092
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 &  _LC052 & 
              _LC090 &  _LC092 & !spdsel_0
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC049 &  _LC052 & 
              _LC090 &  _LC092 & !spdsel_1
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 & !_LC026 &  _LC049 & 
              _LC052 &  _LC090 &  _LC092;

-- Node name is '|toplev:2|ram:132|~299~1' from file "ram.tdf" line 90, column 16
-- Equation name is '_LC025', type is buried 
-- synthesized logic cell 
_LC025   = LCELL( _EQ080 $  GND);
  _EQ080 =  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 &  _LC049 & 
             !_LC050 &  _LC052 & !_LC066 & !_LC081 & !_LC082 &  _LC090 & 
              _LC092
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 &  _LC049 & 
              _LC052 &  _LC090 &  _LC092 & !spdsel_1
         #  _LC012 &  _LC016 &  _LC018 &  _LC022 &  _LC026 &  _LC049 & 
              _LC052 &  _LC090 &  _LC092 & !spdsel_0
         # !_LC026 & !_LC090
         # !_LC016 & !_LC026;

-- Node name is '|toplev:2|ram:132|~299~2' from file "ram.tdf" line 90, column 16
-- Equation name is '_LC007', type is buried 
-- synthesized logic cell 
_LC007   = LCELL( _EQ081 $  GND);
  _EQ081 = !_LC012 & !_LC026
         # !_LC022 & !_LC026
         # !_LC026 & !_LC052
         # !_LC018 & !_LC026
         # !_LC026 & !_LC092;

-- Node name is '|toplev:2|ram:132|REFRESH' = '|toplev:2.Refresh' from file "ram.tdf" line 34, column 18
-- Equation name is '_LC091', type is buried 
_LC091   = DFFE( _EQ082 $  VCC, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ082 =  _LC050 & !_LC066 & !_LC082 & !_LC091
         #  _LC066 &  _LC082 & !_LC091
         # !_LC050 & !_LC082 &  _X047
         #  _LC081 &  _X048;
  _X047  = EXP(!_LC012 & !_LC016 & !_LC018 & !_LC022 & !_LC026 & !_LC049 & 
             !_LC052 & !_LC066 & !_LC090 & !_LC092);
  _X048  = EXP(!_LC050 & !_LC066 &  _LC082);

-- Node name is '|toplev:2|rom:154|COUNTER0' = '|toplev:2|rom:154.ao0' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC063', type is buried 
_LC063   = TFFE( _EQ083, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ083 = !_LC028 & !_LC057 &  _LC063 & !_LC098 & !_LC103
         # !_LC028 &  _LC057 &  _LC063 &  _LC103
         #  _LC028 & !_LC057 & !_LC098 &  _LC103;

-- Node name is '|toplev:2|rom:154|COUNTER1' = '|toplev:2|rom:154.ao1' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC054', type is buried 
_LC054   = TFFE( _EQ084, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ084 =  _LC028 & !_LC057 &  _LC063 & !_LC098 &  _LC103
         # !_LC028 &  _LC054 & !_LC057 & !_LC098 & !_LC103
         # !_LC028 &  _LC054 &  _LC057 &  _LC103;

-- Node name is '|toplev:2|rom:154|COUNTER2' = '|toplev:2|rom:154.ao2' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC107', type is buried 
_LC107   = TFFE( _EQ085, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ085 =  _LC028 &  _LC054 & !_LC057 &  _LC063 & !_LC098 &  _LC103
         # !_LC028 & !_LC057 & !_LC098 & !_LC103 &  _LC107
         # !_LC028 &  _LC057 &  _LC103 &  _LC107;

-- Node name is '|toplev:2|rom:154|COUNTER3' = '|toplev:2|rom:154.ao3' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC047', type is buried 
_LC047   = TFFE( _EQ086, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ086 =  _LC028 &  _LC054 & !_LC057 &  _LC063 & !_LC098 &  _LC103 & 
              _LC107
         # !_LC028 & !_LC047 &  _LC057 &  _LC068 & !_LC098 &  _LC103
         # !_LC028 &  _LC047 &  _LC057 &  _LC103 &  _X049
         # !_LC028 &  _LC047 & !_LC057 & !_LC098 & !_LC103;
  _X049  = EXP( _LC068 & !_LC098);

-- Node name is '|toplev:2|rom:154|COUNTER4' from file "rom.tdf" line 29, column 9
-- Equation name is '_LC034', type is buried 
_LC034   = TFFE( _EQ087, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ087 =  _LC028 &  _LC047 &  _LC054 & !_LC057 &  _LC063 & !_LC098 & 
              _LC103 &  _LC107
         # !_LC028 & !_LC034 &  _LC057 &  _LC070 & !_LC098 &  _LC103
         # !_LC028 &  _LC034 &  _LC057 &  _LC103 &  _X050
         # !_LC028 &  _LC034 & !_LC057 & !_LC098 & !_LC103;
  _X050  = EXP( _LC070 & !_LC098);

-- Node name is '|toplev:2|rom:154|rom_state~1' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC103', type is buried 
_LC103   = DFFE( _EQ088 $  GND, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ088 =  /cs_ram & !_LC057 & !_LC089 & !_LC098 & !_LC103 &  _LC113 & 
              _LC121 &  LTT1
         # !_LC028 & !_LC057 &  _LC098 &  _LC103
         # !_LC057 &  _LC098 & !_LC103 & !spdsel_1
         #  _LC028 & !_LC057 & !_LC103;

-- Node name is '|toplev:2|rom:154|rom_state~2' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC098', type is buried 
_LC098   = TFFE( _EQ089, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ089 =  /cs_ram & !_LC010 & !_LC057 & !_LC089 & !_LC098 & !_LC103 & 
              _LC113 &  _LC121 &  LTT1
         #  _LC028 & !_LC057 & !_LC098 & !_LC103
         # !_LC028 &  _LC098 &  _LC103
         #  _LC057 &  _LC098;

-- Node name is '|toplev:2|rom:154|rom_state~3' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC028', type is buried 
_LC028   = DFFE( _EQ090 $  _EQ091, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ090 =  _LC034 &  _LC047 &  _LC054 & !_LC057 &  _LC063 &  _LC098 & 
              _LC103 &  _LC107 &  _X051 &  _X052 &  _X053 &  _X054
         #  _LC010 &  _LC054 & !_LC057 &  _LC063 &  _LC098 &  _LC103 & 
              _LC107 &  _X051 &  _X052 &  _X053 &  _X054
         #  _LC098 & !_LC103 & !spdsel_1 &  _X051 &  _X052 &  _X053 &  _X054;
  _X051  = EXP(!_LC028 & !_LC057 & !_LC098);
  _X052  = EXP( _LC028 &  _LC057);
  _X053  = EXP( _LC028 &  _LC098);
  _X054  = EXP( _LC057 & !_LC103);
  _EQ091 =  _X051 &  _X052 &  _X053 &  _X054;
  _X051  = EXP(!_LC028 & !_LC057 & !_LC098);
  _X052  = EXP( _LC028 &  _LC057);
  _X053  = EXP( _LC028 &  _LC098);
  _X054  = EXP( _LC057 & !_LC103);

-- Node name is '|toplev:2|rom:154|rom_state~4' from file "rom.tdf" line 23, column 2
-- Equation name is '_LC057', type is buried 
_LC057   = DFFE( _EQ092 $  GND, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ092 =  /cs_ram & !_LC028 & !_LC057 & !_LC089 & !_LC098 & !_LC103 & 
              _LC113 &  _LC121 &  LTT1;

-- Node name is '|toplev:2|3mux:177|~57~1' = '|toplev:2|3mux~177.done~1' from file "3mux.tdf" line 27, column 8
-- Equation name is '_LC101', type is buried 
-- synthesized logic cell 
_LC101   = LCELL( _EQ093 $  GND);
  _EQ093 =  /cs_ram & !_LC028 &  _LC054 & !_LC057 &  _LC063 & !_LC086 & 
              _LC098 &  _LC103 &  _LC107 &  _LC113
         #  /cs_ram & !_LC039 & !_LC059 &  _LC060 & !_LC086 &  _LC108 & 
             !_LC113
         #  /cs_ram & !_LC039 &  _LC059 & !_LC060 & !_LC086 & !_LC108 & 
             !_LC113
         # !/cs_ram &  _LC050 & !_LC066 &  _LC081 & !_LC082 & !_LC086
         #  _LC086 &  _LC089 & !_LC121;

-- Node name is '|toplev:2|3mux:177|~61~1' = '|toplev:2|3mux~177.lastta~1' from file "3mux.tdf" line 29, column 10
-- Equation name is '_LC112', type is buried 
-- synthesized logic cell 
_LC112   = LCELL( _EQ094 $  GND);
  _EQ094 =  /cs_ram & !_LC028 & !_LC033 & !_LC057 & !_LC098 &  _LC103 & 
              _LC113
         #  /cs_ram & !_LC033 & !_LC039 & !_LC059 &  _LC060 &  _LC108 & 
             !_LC113
         #  /cs_ram & !_LC033 & !_LC039 &  _LC059 & !_LC060 & !_LC108 & 
             !_LC113
         # !/cs_ram & !_LC033 &  _LC050 & !_LC066 & !_LC081 & !_LC082 & 
             !_LC091
         #  _LC033 & !_LC089 & !_LC121;

-- Node name is '|toplev:2|:126' 
-- Equation name is '_LC097', type is buried 
_LC097   = TFFE( _EQ095, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);
  _EQ095 =  /cs_ram &  _LC039 & !_LC059 & !_LC060 & !_LC097 &  _LC108 & 
             !_LC113
         #  /cs_ram & !_LC028 &  _LC057 & !_LC097 &  _LC103 &  _LC113
         # !/cs_ram &  _LC050 & !_LC066 &  _LC081 &  _LC082 & !_LC097
         #  _LC089 &  _LC097 &  _LC121;

-- Node name is '|toplev:2|:181' 
-- Equation name is '_LC086', type is buried 
_LC086   = TFFE( _LC101, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);

-- Node name is '|toplev:2|:182' 
-- Equation name is '_LC033', type is buried 
_LC033   = TFFE( _LC112, GLOBAL( 2xpclk),  /reset,  VCC,  VCC);

-- Node name is '|toplev:2|:184' 
-- Equation name is '_LC010', type is buried 
_LC010   = DFFE( /tbst $  GND,  _EQ096,  VCC,  VCC,  VCC);
  _EQ096 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '|601sim:1|601state:1|ABB' from file "601state.tdf" line 9, column 28
-- Equation name is '_LC079', type is buried 
_LC079   = DFFE( _EQ097 $  VCC, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ097 = !_LC072 &  _LC076 & !_LC078 &  _LC079 &  /ts
         # !_LC079 &  _LC119 &  /ts;

-- Node name is '|601sim:1|601state:1|olap' from file "601state.tdf" line 31, column 28
-- Equation name is '_LC114', type is buried 
_LC114   = DFFE( _EQ098 $ !/dbb, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ098 = !/dbb & !_LC114 &  /ts;

-- Node name is '|601sim:1|601state:1|split~' = '|601sim:1|601state:1.split' from file "601state.tdf" line 9, column 37
-- Equation name is '_LC119', type is buried 
_LC119   = DFFE( _EQ099 $  VCC, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ099 =  _LC116 & !_LC119 &  _LC127
         #  _LC124 &  _LC127
         #  _LC079 & !_LC119
         # !_LC079 & !/ts;

-- Node name is '|601sim:1|601state:1|ta0' from file "601state.tdf" line 19, column 28
-- Equation name is '_LC116', type is buried 
_LC116   = TFFE( _EQ100, GLOBAL( pclk),  VCC,  /reset,  VCC);
  _EQ100 =  _LC089 &  _LC116 & !_LC121 & !_LC124 &  /tbst
         #  _LC089 & !_LC116 & !_LC121 &  _LC124 & !_LC127
         #  _LC116 &  _LC127;

-- Node name is '|601sim:1|601state:1|ta1' from file "601state.tdf" line 19, column 33
-- Equation name is '_LC124', type is buried 
_LC124   = TFFE( _EQ101, GLOBAL( pclk),  /reset,  VCC,  VCC);
  _EQ101 =  _LC089 &  _LC116 & !_LC121 & !_LC127
         #  _LC089 & !_LC116 & !_LC121 & !_LC124
         #  _LC124 &  _LC127;

-- Node name is '|601sim:1|601state:1|ta2' from file "601state.tdf" line 19, column 38
-- Equation name is '_LC127', type is buried 
_LC127   = TFFE( _EQ102, GLOBAL( pclk),  VCC,  /reset,  VCC);
  _EQ102 = !_LC116 & !_LC119 & !_LC124 & !_LC127 & !/tbst &  _X055
         # !_LC116 &  _LC124 &  _LC127 &  /tbst
         #  _LC089 & !_LC121 & !_LC124 &  _X056
         #  _LC116 & !_LC124 &  _LC127;
  _X055  = EXP( _LC089 & !_LC121);
  _X056  = EXP(!_LC116 & !_LC119 & !_LC127 & !/tbst);

-- Node name is '/aack' 
-- Equation name is '/aack', location is LC005, type is output.
 /aack   = LCELL( _EQ103 $  VCC);
  _EQ103 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '/cas0' 
-- Equation name is '/cas0', location is LC008, type is output.
 /cas0   = LCELL( _EQ104 $  VCC);
  _EQ104 =  _LC042 & !_LC068 & !_LC070 & !_LC071
         #  _LC042 &  _LC091
         # !_LC010 &  _LC042;

-- Node name is '/cas1' 
-- Equation name is '/cas1', location is LC003, type is output.
 /cas1   = LCELL( _EQ105 $ !_LC042);
  _EQ105 =  _LC010 &  _LC042 & !_LC071 &  _LC073 & !_LC074 & !_LC091 & 
             !_LC122
         #  _LC010 &  _LC042 &  _LC071 & !_LC073 & !_LC074 & !_LC091 & 
             !_LC122
         #  _LC010 &  _LC042 &  _LC068 & !_LC091
         #  _LC010 &  _LC042 &  _LC070 & !_LC091;

-- Node name is '/cas2' 
-- Equation name is '/cas2', location is LC099, type is output.
 /cas2   = LCELL( _EQ106 $  _EQ107);
  _EQ106 =  _LC042 & !_LC068 & !_LC071 &  _LC073 & !_LC074 &  _LC122 &  _X057 & 
              _X058 &  _X059 &  _X060 &  _X061
         #  _LC042 & !_LC068 &  _LC070 & !_LC071 &  _LC073 & !_LC122 &  _X057 & 
              _X058 &  _X059 &  _X060 &  _X061
         #  _LC042 & !_LC068 &  _LC070 & !_LC071 & !_LC073 &  _LC122 &  _X057 & 
              _X058 &  _X059 &  _X060 &  _X061
         #  _LC042 & !_LC068 & !_LC070 & !_LC071 & !_LC073 & !_LC122 &  _X057 & 
              _X058 &  _X059 &  _X060 &  _X061;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X059  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074);
  _X060  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC071 &  _LC122);
  _X061  = EXP( _LC042 & !_LC068 & !_LC071 &  _LC074 & !_LC122);
  _EQ107 =  _X057 &  _X058 &  _X059 &  _X060 &  _X061;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X059  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074);
  _X060  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC071 &  _LC122);
  _X061  = EXP( _LC042 & !_LC068 & !_LC071 &  _LC074 & !_LC122);

-- Node name is '/cas3' 
-- Equation name is '/cas3', location is LC105, type is output.
 /cas3   = LCELL( _EQ108 $  _EQ109);
  _EQ108 =  _LC042 & !_LC068 &  _LC071 &  _LC073 & !_LC074 &  _LC122 &  _X057 & 
              _X058 &  _X059 &  _X062 &  _X063
         #  _LC042 & !_LC068 &  _LC070 &  _LC071 &  _LC073 & !_LC122 &  _X057 & 
              _X058 &  _X059 &  _X062 &  _X063
         #  _LC042 & !_LC068 & !_LC070 & !_LC071 & !_LC073 & !_LC122 &  _X057 & 
              _X058 &  _X059 &  _X062 &  _X063
         #  _LC042 & !_LC068 &  _LC070 & !_LC074 &  _LC122 &  _X057 &  _X058 & 
              _X059 &  _X062 &  _X063;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X059  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074);
  _X062  = EXP( _LC042 & !_LC068 & !_LC071 & !_LC073 &  _LC074);
  _X063  = EXP( _LC042 & !_LC068 &  _LC074 & !_LC122);
  _EQ109 =  _X057 &  _X058 &  _X059 &  _X062 &  _X063;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X059  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074);
  _X062  = EXP( _LC042 & !_LC068 & !_LC071 & !_LC073 &  _LC074);
  _X063  = EXP( _LC042 & !_LC068 &  _LC074 & !_LC122);

-- Node name is '/cas4' 
-- Equation name is '/cas4', location is LC011, type is output.
 /cas4   = LCELL( _EQ110 $  _EQ111);
  _EQ110 = !_LC001 &  _LC042 &  _LC068 & !_LC070 & !_LC071 & !_LC073 & 
              _LC074 & !_LC122 &  _X057 &  _X058 &  _X064 &  _X065
         # !_LC001 &  _LC042 & !_LC068 & !_LC070 & !_LC071 & !_LC073 & 
             !_LC074 & !_LC122 &  _X057 &  _X058 &  _X064 &  _X065
         # !_LC001 &  _LC042 & !_LC068 &  _LC070 &  _LC073 & !_LC074 & 
              _LC122 &  _X057 &  _X058 &  _X064 &  _X065
         # !_LC001 &  _LC042 & !_LC068 &  _LC070 &  _LC071 & !_LC074 & 
              _LC122 &  _X057 &  _X058 &  _X064 &  _X065;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X064  = EXP( _LC042 & !_LC068 &  _LC070 &  _LC074 & !_LC122);
  _X065  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074 &  _LC122);
  _EQ111 = !_LC001 &  _X057 &  _X058 &  _X064 &  _X065;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X064  = EXP( _LC042 & !_LC068 &  _LC070 &  _LC074 & !_LC122);
  _X065  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074 &  _LC122);

-- Node name is '/cas5' 
-- Equation name is '/cas5', location is LC013, type is output.
 /cas5   = LCELL( _EQ112 $  _EQ113);
  _EQ112 =  _LC042 & !_LC068 &  _LC070 &  _LC071 &  _LC073 & !_LC074 & 
              _LC122 &  _X057 &  _X058 &  _X064 &  _X065 &  _X066 &  _X067 & 
              _X068
         #  _LC042 &  _LC068 & !_LC070 & !_LC071 & !_LC073 &  _LC074 & 
             !_LC122 &  _X057 &  _X058 &  _X064 &  _X065 &  _X066 &  _X067 & 
              _X068
         #  _LC042 & !_LC068 & !_LC070 & !_LC071 & !_LC073 & !_LC074 & 
             !_LC122 &  _X057 &  _X058 &  _X064 &  _X065 &  _X066 &  _X067 & 
              _X068
         #  _LC042 & !_LC068 & !_LC070 &  _LC071 &  _LC073 &  _LC074 &  _X057 & 
              _X058 &  _X064 &  _X065 &  _X066 &  _X067 &  _X068;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X064  = EXP( _LC042 & !_LC068 &  _LC070 &  _LC074 & !_LC122);
  _X065  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074 &  _LC122);
  _X066  = EXP( _LC042 &  _LC068 & !_LC070 &  _LC071 &  _LC073 & !_LC074);
  _X067  = EXP( _LC042 & !_LC068 &  _LC070 & !_LC071 & !_LC073 &  _LC074);
  _X068  = EXP( _LC042 &  _LC068 & !_LC070 & !_LC074 &  _LC122);
  _EQ113 =  _X057 &  _X058 &  _X064 &  _X065 &  _X066 &  _X067 &  _X068;
  _X057  = EXP( _LC042 &  _LC091);
  _X058  = EXP(!_LC010 &  _LC042);
  _X064  = EXP( _LC042 & !_LC068 &  _LC070 &  _LC074 & !_LC122);
  _X065  = EXP( _LC042 & !_LC068 & !_LC070 &  _LC074 &  _LC122);
  _X066  = EXP( _LC042 &  _LC068 & !_LC070 &  _LC071 &  _LC073 & !_LC074);
  _X067  = EXP( _LC042 & !_LC068 &  _LC070 & !_LC071 & !_LC073 &  _LC074);
  _X068  = EXP( _LC042 &  _LC068 & !_LC070 & !_LC074 &  _LC122);

-- Node name is '/cas6' 
-- Equation name is '/cas6', location is LC067, type is output.
 /cas6   = LCELL( _EQ114 $  _EQ115);
  _EQ114 =  _LC010 &  _LC042 &  _LC068 &  _LC070 & !_LC071 &  _LC073 & 
             !_LC074 & !_LC091 & !_LC102 & !_LC122 &  _X057 &  _X069 &  _X070 & 
              _X071 &  _X072
         #  _LC010 &  _LC042 &  _LC068 &  _LC070 & !_LC071 & !_LC073 & 
             !_LC074 & !_LC091 & !_LC102 &  _LC122 &  _X057 &  _X069 &  _X070 & 
              _X071 &  _X072
         #  _LC010 &  _LC042 &  _LC068 & !_LC070 & !_LC071 &  _LC073 & 
             !_LC074 & !_LC091 & !_LC102 &  _LC122 &  _X057 &  _X069 &  _X070 & 
              _X071 &  _X072
         #  _LC010 &  _LC042 & !_LC068 &  _LC070 & !_LC071 &  _LC073 & 
              _LC074 & !_LC091 & !_LC102 & !_LC122 &  _X057 &  _X069 &  _X070 & 
              _X071 &  _X072;
  _X057  = EXP( _LC042 &  _LC091);
  _X069  = EXP( _LC010 &  _LC042 & !_LC068 & !_LC070 & !_LC071 &  _LC073 & 
              _LC074 & !_LC091 &  _LC122);
  _X070  = EXP( _LC010 &  _LC042 &  _LC068 & !_LC070 &  _LC071 & !_LC074 & 
             !_LC091 &  _LC122);
  _X071  = EXP( _LC010 &  _LC042 & !_LC068 &  _LC070 &  _LC071 &  _LC074 & 
             !_LC091 & !_LC122);
  _X072  = EXP( _LC010 &  _LC042 & !_LC068 & !_LC070 &  _LC071 &  _LC074 & 
             !_LC091 &  _LC122);
  _EQ115 = !_LC102 &  _X057 &  _X069 &  _X070 &  _X071 &  _X072;
  _X057  = EXP( _LC042 &  _LC091);
  _X069  = EXP( _LC010 &  _LC042 & !_LC068 & !_LC070 & !_LC071 &  _LC073 & 
              _LC074 & !_LC091 &  _LC122);
  _X070  = EXP( _LC010 &  _LC042 &  _LC068 & !_LC070 &  _LC071 & !_LC074 & 
             !_LC091 &  _LC122);
  _X071  = EXP( _LC010 &  _LC042 & !_LC068 &  _LC070 &  _LC071 &  _LC074 & 
             !_LC091 & !_LC122);
  _X072  = EXP( _LC010 &  _LC042 & !_LC068 & !_LC070 &  _LC071 &  _LC074 & 
             !_LC091 &  _LC122);

-- Node name is '/cas7' 
-- Equation name is '/cas7', location is LC075, type is output.
 /cas7   = LCELL( _EQ116 $  _EQ117);
  _EQ116 =  _LC010 &  _LC042 &  _LC068 &  _LC070 &  _LC071 &  _LC073 & 
             !_LC074 & !_LC091 & !_LC102 & !_LC122 &  _X057 &  _X073
         #  _LC010 &  _LC042 &  _LC068 & !_LC070 &  _LC071 &  _LC073 & 
             !_LC074 & !_LC091 & !_LC102 &  _LC122 &  _X057 &  _X073
         #  _LC010 &  _LC042 & !_LC068 &  _LC070 &  _LC071 &  _LC073 & 
              _LC074 & !_LC091 & !_LC102 & !_LC122 &  _X057 &  _X073
         #  _LC010 &  _LC042 & !_LC068 & !_LC070 &  _LC071 &  _LC073 & 
              _LC074 & !_LC091 & !_LC102 &  _LC122 &  _X057 &  _X073;
  _X057  = EXP( _LC042 &  _LC091);
  _X073  = EXP( _LC010 &  _LC042 &  _LC068 &  _LC070 & !_LC071 & !_LC073 & 
             !_LC074 & !_LC091 &  _LC122);
  _EQ117 = !_LC102 &  _X057 &  _X073;
  _X057  = EXP( _LC042 &  _LC091);
  _X073  = EXP( _LC010 &  _LC042 &  _LC068 &  _LC070 & !_LC071 & !_LC073 & 
             !_LC074 & !_LC091 &  _LC122);

-- Node name is '/cs_io' 
-- Equation name is '/cs_io', location is LC093, type is output.
 /cs_io  = LCELL( _EQ118 $  VCC);
  _EQ118 =  /cs_ram & !_LC113;

-- Node name is '/cs_ram' = '|adrlatch:7|74374:3|:13' 
-- Equation name is '/cs_ram', type is output 
 /cs_ram = DFFE( adr0 $  GND,  _EQ119,  VCC,  VCC,  VCC);
  _EQ119 = !_LC072 &  _LC076 & !_LC078;

-- Node name is '/cs_rom' 
-- Equation name is '/cs_rom', location is LC083, type is output.
 /cs_rom = LCELL( _EQ120 $  VCC);
  _EQ120 =  /cs_ram &  _LC113;

-- Node name is '/dbb' = '|601sim:1|601state:1|DBB' from file "601state.tdf" line 31, column 34
-- Equation name is '/dbb', type is output 
/dbb     = _LC125~NOT;
_LC125~NOT = DFFE( _EQ121 $  GND, GLOBAL( pclk),  VCC,  /reset,  VCC);
  _EQ121 = !/dbb &  _LC089 & !_LC121 & !_LC124 & !_LC127
         #  /dbb & !_LC114 &  /ts;

-- Node name is '/g0' = '|toplev:2./G0' 
-- Equation name is '/g0', type is output 
 /g0     = LCELL( /dbb $  GND);

-- Node name is '/ras' = '|toplev:2|ram:132|RAS_FF' from file "ram.tdf" line 34, column 2
-- Equation name is '/ras', type is output 
/ras     = _LC032~NOT;
_LC032~NOT = DFFE( _EQ122 $  GND, GLOBAL( 2xpclk),  VCC,  /reset,  VCC);
  _EQ122 =  _LC050 &  _LC066 &  _LC081 &  _LC082
         # !_LC050 & !_LC066 &  _LC081 &  _LC082
         # !_LC050 & !_LC081 & !_LC082
         # !_LC066 & !_LC081 & !_LC082;

-- Node name is '/ta' 
-- Equation name is '/ta', location is LC088, type is output.
 /ta     = LCELL( _EQ123 $  VCC);
  _EQ123 =  _LC089 & !_LC121;

-- Node name is '/tbst' = '|601sim:1|601cycle:13|tbst' from file "601cycle.tdf" line 31, column 16
-- Equation name is '/tbst', type is output 
/tbst    = _LC118~NOT;
_LC118~NOT = TFFE( _EQ124, GLOBAL( pclk),  VCC,  VCC,  VCC);
  _EQ124 =  adr0 & !_LC079 & !_LC119 &  /reset &  /tbst &  tt1
         # !_LC079 & !_LC119 & !/tbst &  /ts &  tt1
         #  adr0 & !adr1 & !/tbst
         #  adr0 & !/tbst & !tt1
         # !/reset & !/tbst;

-- Node name is '/ts' = '|601sim:1|601state:1|TS' from file "601state.tdf" line 9, column 33
-- Equation name is '/ts', type is output 
/ts      = _LC080~NOT;
_LC080~NOT = DFFE( _LC079 $  _EQ125, GLOBAL( pclk),  VCC,  /reset,  VCC);
  _EQ125 = !_LC079 &  _LC119 &  /ts;

-- Node name is '/we_ram' 
-- Equation name is '/we_ram', location is LC053, type is output.
 /we_ram = LCELL( _EQ126 $  VCC);
  _EQ126 =  _LC081 & !_LC082 & !LTT1;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X019 occurs in LABs ----EF--
--    _X036 occurs in LABs ---D-F--
--    _X057 occurs in LABs A---E-G-
--    _X058 occurs in LABs A-----G-




Project Information                                             c:\bean\mb.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000E' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic I/O Cell Registers        = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interface Menu Commands
-----------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:21
   Database Builder                       00:00:26
   Logic Synthesizer                      00:00:55
   Partitioner                            00:00:09
   Fitter                                 00:00:30
   Timing SNF Extractor                   00:00:18
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:02:41


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,253K
